W144
Document #: 38-07153 Rev. *B
Page 3 of 14
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3:..................................................................... 3.3V±5%
VDDQ2:..................................................................... 2.5V±5%
SDRAMIN to SDRAM0:11 Delay: ......................... 3.7 ns typ.
SDRAM0:11 (leads) to SDRAM_F Skew: ............. 0.4 ns typ.
Overview
The W144 was developed as a single-chip device to meet the
clocking needs of the Intel 440BX AGPset. In addition to the
typical outputs provided by standard 100-MHz 440BX FTGs,
the W144 adds a thirteen output buffer, supporting SDRAM
DIMM modules in conjunction with the chipset.
Cypress’s proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. When
enabled, this feature reduces the peak EMI measurements of
not only the output signals and their harmonics, but also of any
other clock signals that are properly synchronized to them.
Functional Description
I/O Pin Operation
Pins 7, 8, 25, 26, and 46 are dual-purpose l/O pins. Upon
power-up these pins act as logic inputs, allowing the determi-
nation of assigned device functions. A short time after
power-up, the logic state of each pin is latched and the pins
become clock outputs. This feature reduces device pin count
by combining clock outputs with input select pins.
An external 10-k
Ω “strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W144 power up, the first 2 ms of operation is used for
input logic selection. During this period, the five I/O pins (7, 8,
25, 26, 46) are three-stated, allowing the output strapping
resistor on the l/O pins to pull the pin and their associated
capacitive clock load to either a logic HIGH or LOW state. At
the end of the 2ms period, the established logic “0” or “1”
condition of the l/O pin is latched. Next the output buffer is
enabled converting the l/O pins into operating clock outputs.
The 2-ms timer starts when VDD reaches 2.0V. The input bits
can only be reset by turning VDD off and then back on again.
It should be noted that the strapping resistors have no signif-
icant effect on clock output signal integrity. The drive
impedance of clock outputs are <40
Ω (nominal) which is
minimally affected by the 10-k
Ω strap to ground or VDD. As
with the series termination resistor, the output strapping
resistor should be placed as close to the l/O pin as possible in
order to keep the interconnecting trace short. The trace from
the resistor to ground or VDD should be kept less than two
inches in length to prevent system noise coupling during input
logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that VDD has stabilized. If VDD has not yet reached
full value, output frequency initially may be below target but will
increase to target once VDD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
Table 2. Mode Input Table
Mode
Pin2
0PCI_STOP#
1REF0
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W144
VDD
Clock Load
10 k
Ω
Output
Buffer
(Load Option 1)
10 k
Ω
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
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