PRELIMINARY
CYU01M16ZCC
MoBL3™
Document #: 38-05602 Rev. *F
Page 8 of 14
Switching Characteristics Over the Operating Range[12, 13, 14, 15, 18]
Parameter
Description
70 ns
Unit
Min.
Max.
Read Cycle
tRC [17]
Read Cycle Time
70
40000
ns
tCD
Chip Deselect Time
CE, BLE/BHE High Pulse Time
15
ns
tAA
Address to Data Valid
70
ns
tOHA
Data Hold from Address Change
5
ns
tACE
CE LOW to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
tLZOE
OE LOW to Low Z[13, 14, 16]
5ns
tHZOE
OE HIGH to High Z[13, 14, 16]
25
ns
tLZCE
CE LOW to Low Z[13, 14, 16]
10
ns
tHZCE
CE HIGH to High Z[13, 14, 16]
25
ns
tDBE
BLE/BHE LOW to Data Valid
70
ns
tLZBE
BLE/BHE LOW to Low Z[13, 14, 16]
5ns
tHZBE
BLE/BHE HIGH to High Z[13, 14, 16]
25
ns
Page Read Cycle
tPC
Page Mode Read Cycle Time
35
40000
ns
tPA
Page Mode Address Access
35
ns
Write Cycle[15]
tWC
Write Cycle Time
70
40000
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-Up to Write End
60
ns
tCD
Chip Deselect Time
CE, BLE/BHE High Pulse Time
15
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
50
ns
tBW
BLE/BHE LOW to Write End
60
ns
tSD
Data Set-Up to Write End
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
WE LOW to High-Z[13, 14, 16]
25
ns
tLZWE
WE HIGH to Low-Z[13, 14, 16]
10
ns
Notes:
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC/2, input pulse levels of
0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
13. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V)
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write
16. High-Z and Low-Z parameters are characterized and are not 100% tested.
17. If invalid address signals shorter than min.tRC are continuously repeated for 40us, the device needs a normal read timing (tRC) or needs to enter standby state
at least once in every 40
µs.
18. In order to achieve 70-ns performance, the read access must be CE controlled. That is, the addresses must be stable prior to CE going active.
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