CYV15G0101DXB
CYW15G0101DXB
CYP15G0101DXB
Document #: 38-02031 Rev. *J
Page 6 of 39
TXRST
LVTTL Input,
asynchronous,
internal pull-up,
sampled by
REFCLK
↑[3]
Transmit Clock Phase Reset. Active LOW. When sampled LOW, the transmit Phase-align
Buffer is allowed to adjust its data-transfer timing (relative to the selected input clock) to
allow clean transfer of data from the Input Register to the Encoder or Transmit Shifter. When
TXRST is sampled HIGH, the internal phase relationship between the TXCLK and the
internal character-rate clock is fixed and the device operates normally.
When configured for half-rate REFCLK sampling of the transmit character stream
(TXCKSEL = LOW and TXRATE = HIGH), assertion of TXRST is only used to clear
Phase-align buffer faults caused by highly asymmetric reference clock periods or reference
clocks with excessive cycle-to-cycle jitter. During this alignment period, one or more
characters may be added to or lost from all the associated transmit paths as the transmit
Phase-align Buffers are adjusted. TXRST must be sampled LOW by a minimum of two
consecutive rising edges of REFCLK to ensure the reset operation is initiated correctly on
all channels. This input is ignored when both TXCKSEL and TXRATE are LOW, since the
phase align buffer is bypassed. In all other configurations, TXRST should be asserted during
device initialization to ensure proper operation of the Phase-align buffer. TXRST should be
asserted after the assertion and deassertion of TRSTZ, after the presence of a valid TXCLK
and after allowing enough time for the TXPLL to lock to the reference clock (as specified by
parameter tTXLOCK).
Transmit Path Clock and Clock Control
TXCKSEL
3-Level Select static
control input[4]
Transmit Clock Select. Selects the clock source used to write data into the Transmit Input
Register of the transmit channel. When LOW, the Input Register is clocked by REFCLK
↑.[3]
When HIGH or MID, TXCLK
↑ is the Input Register clock for TXD[7:0] and TXCT[1:0].
When TXRATE=HIGH, configuring TXCKSEL = HIGH or MID is an invalid mode of
operation.
TXCLKO
±
LVTTL Output
Transmit Clock Output. This true and complement output clock is synthesized by the
transmit PLL and is synchronous to the internal transmit character clock. It has the same
frequency as REFCLK (when TXRATE = LOW), or twice the frequency of REFCLK (when
TXRATE = HIGH). This output clock has no direct phase relationship to REFCLK.
TXRATE
LVTTL Input,
Static Control input,
internal pull-down
Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multiplies
REFCLK by 20 to generate the serial bit-rate clock.
When TXRATE = LOW, the transmit PLL multiplies REFCLK by 10 to generate the serial
bit-rate clock. See Table 9 for a list of operating serial rates.
When REFCLK is selected to clock the receive parallel interfaces (RXCKSEL = LOW), the
TXRATE input also determines if the clocks on the RXCLK
± and RXCLKC+ outputs are full
or half-rate. When TXRATE = HIGH (REFCLK is half-rate), the RXCLK± and RXCLKC+
output clocks are also half-rate clocks and follow the frequency and duty cycle of the
REFCLK input. When TXRATE = LOW (REFCLK is full-rate), the RXCLK± and RXCLKC+
output clocks are also full-rate clocks and follow the frequency and duty cycle of the
REFCLK input.
When TXRATE=HIGH, configuring TXCKSEL = HIGH or MID is an invalid mode of
operation.
TXCLK
LVTTL Clock Input,
internal pull-down
Transmit Path Input Clock. This clock must be frequency-coherent to TXCLKO
±, but may
be offset in phase. The internal operating phase of the input clock (relative to REFLCK or
TXCLKO+) is adjusted when TXRST = LOW and locked when TXRST =HIGH.
Transmit Path Mode Control
TXMODE[1:0] 3-Level Select[4]
static control inputs
Transmit Operating Mode. These inputs are interpreted to select one of nine operating
modes of the transmit path. See Table 3 for a list of operating modes.
Note:
4.
3-Level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH.
The LOW level is usually implemented by direct connection to VSS (ground). The HIGH level is usually implemented by direct connection to VCC (power). When
not connected or allowed to float, a 3-Level select input will self-bias to the MID level.
Pin Descriptions CYP(V)(W)15G0101DXB Single-channel HOTLink II (continued)
Pin Name
I/O Characteristics Signal Description
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