CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 10 of 153
1.0
Features
• Up to 512K 36-bit entries in a single device for CYNSE10512
— 256K entries in 72-bit configuration
— 128K entries in 144-bit configuration
— 64K entries in 288-bit configuration
— 32K entries in 576-bit configuration
•Up to 256K 36-bit entries in a single device for CYNSE10256
— 128K entries in 72-bit configuration
— 64K entries in 144-bit configuration
— 32K entries in 288-bit configuration
— 16K entries in 576-bit configuration
•Up to 128K 36-bit entries in a single device for CYNSE10128
— 64K entries in 72-bit configuration
— 32K entries in 144-bit configuration
— 16K entries in 288-bit configuration
— 8K entries in 576-bit configuration
• Multiple width tables in a single device
• Single-cycle Search operation on 72-/144-bit tables
• Mini-Key
-programmable search key for fine grain table selection and power conservation
• Prioritized blocks with no overhead in table management using programmable Soft Priority
• Parity support for reliable operation
• Non-Enhanced Mode and Enhanced Mode operation
— Up to 133 million searches per second in 72-/144-bit configuration
— Up to 66.5 million searches per second in 36-/288-bit configuration
— Up to 33.25 million searches per second in 576-bit configuration (Enhanced Mode Only)
• Enhanced Mode with MultiSearch
operation
— Up to 266 million searches per second in 72-/144-bit configuration
— Up to 133 million searches per second in 36-/288-bit configuration
— Up to 66.5 million searches per second in 576-bit configuration
• Cascadable for depth expansion
• Glueless interface to industry-standard SRAMs and SSRAMs
• Simple hardware instruction interface
• IEEE 1149.1 test access port
• 1.2V core voltage supply
• Supports 1.5V HSTL and 1.8V/2.5V LVCMOS I/O Standards
• 388-pin BGA package
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