5 / 12 page
CY62127DV20
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05301 Rev. **
Page 5 of 12
AC Test Loads and Waveforms
Data Retention Characteristics
Data Retention Waveform[7]
Notes:
6. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
7. BHE
.
BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both.
Parameter
Description
Conditions
Min.
Typ.[4]
Max.
Unit
VDR
VCC for Data Retention
1
2.2
V
ICCDR
Data Retention Current
VCC = 1V, CE1 > VCC − 0.2V, CE2 <
0.2V, VIN > VCC − 0.2V or VIN < 0.2V
L1
µA
LL
TBD
tCDR
[5]
Chip Deselect to Data Reten-
tion Time
0ns
tR
[6]
Operation Recovery Time
tRC
ns
VCC Typ
VCC
UTPUT
R2
C = 30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
Equivalent to:
THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Rise Time:
1 V/ns
Fall Time:
1 V/ns
L
Parameters
1.8V
UNIT
R 1
1350 0
Ω
R 2
1080 0
Ω
R
TH
6000
Ω
V
TH
0.80
V
VCC(min.)
VCC(min.)
tCDR
VDR > 1.0V
DATA RETENTION MODE
tR
CE1 or
VCC
BHE .BLE
CE2
or
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