2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
CY29774
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07479 Rev. **
Revised April 28, 2003
774
Features
• Output frequency range: 8.3 MHz to 125 MHz
• Input frequency range: 4.2 MHz to 62.5 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• 14 Clock outputs: Drive up to 28 clock lines
• 1 Feedback clock output
• 2 LVCMOS reference clock inputs
• 150 ps max output-output skew
• PLL bypass mode
• Spread Aware™
• Output enable/disable
• Pin compatible with MPC9774
• Industrial temperature range: –40°C to +85°C
• 52-Pin 1.0-mm TQFP package
Description
The CY29774 is a low-voltage high-performance 125-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications.
The CY29774 features two reference clock inputs and pro-
vides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs.
Bank A and Bank B divide the VCO output by 4 or 8 while Bank
C divides by 8 or 12 per SEL(A:C) settings, see Functional
Table. These dividers allow output to input ratios of 6:1, 4:1,
3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible out-
put can drive 50
Ω series or parallel terminated transmission
lines. For series terminated transmission lines, each output
can drive one or two traces giving the device an effective
fanout of 1:28.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8.3 MHz to 125 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback di-
vider, see Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
PL L
20 0 -
5 00M H z
÷2 / ÷4
÷4 / ÷6 / ÷8 / ÷12
QA 0
QB 0
QC0
FB_O U T
SE L A
VC O _SE L
TC LK 0
TC LK _ S EL
FB _IN
SELB
SELC
MR #/O E
FB_SEL(1,0)
TC LK 1
÷2
CL K
STO P
÷2 / ÷4
CL K
STO P
÷4 / ÷6
CL K
STO P
C LK_ S T P#
QA 1
QA 2
QA 3
QA 4
QB 1
QB 2
QB 3
QB 4
QC1
QC2
QC3
PL L_ E N
÷4
VSS
MR#/O E
CLK_STP#
SELB
SELC
PLL_EN
SELA
TCLK_SEL
TCLK0
TCLK1
NC
VDD
AVDD
VSS
QB1
VDDQ B
QB2
VSS
QB3
VDDQ B
QB4
FB_IN
VSS
FB_OUT
VDDFB
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
CY29774
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