PRELIMINARY
CY28439-2
Document #: 38-07750 Rev. *B
Page 5 of 22
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
1
RESERVED
RESERVED
6
1
SRC[T/C]4
SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
5
1
SRC[T/C]3
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
4
1
SATA[T/C]
SATA[T/C] Output Enable
0 = Disable (Tri-state), 1 = Enable
3
1
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
2
1
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
1
1
RESERVED
RESERVED
0
1
SRC[T/C]0
SRC[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
1
DOT_96[T/C]
DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
5
1
24_48M
24_48 MHz Output Enable
0 = Disabled, 1 = Enabled
4
1
REF0
REF0 Output Enable
0 = Disabled, 1 = Enabled
3
0
RESERVED
RESERVED
2
1
CPU[T/C]1
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
1
1
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
0
1
CPU
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
6
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
5
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
3
1
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
2
1
PCI0
PCI0 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCIF2
PCIF2 Output Enable
0 = Disabled, 1 = Enabled