1 / 17 page
Clock Synthesizer with Differential SRC and
CPU Outputs
CY28409
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-07445 Rev. *D
Revised January 2, 2006
Features
• Supports Intel® Pentium® 4-type CPUs
• Selectable CPU frequencies
• 3.3V power supply
• Ten copies of PCI clocks
• Five copies of 3V66 with one optional VCH
• Two copies 48-MHz USB clocks
• Three differential CPU clock pairs
• One differential SRC clock
•I2C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
EMI reduction
• 56-pin SSOP and TSSOP packages
Note:
1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
CPU
SRC
3V66
PCI
REF
48M
x 3
x 1
x 5
x 10
x 2
x 2
Block Diagram
Pin Configuration
REF_0
REF_1
XIN
XOUT
VSS_REF
PCIF0
PCIF1
PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
VSS_PCI
PCI4
PCI5
PCI6
PD#
3V66_0
3V66_1
VDD_3V66
VSS_3V66
FS_B
VDD_A
SDATA
VDD_SRC
SRCT
SRCC
VSS_SRC
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
VSS_CPU
CPUT2
CPUC2
VDD_CPU
CPU_STP#
FS_A
VSS_IREF
IREF
VSS_A
VTT_PWRGD#
3V66_2
3V66_3
SCLK
VDD_48
VSS_48
USB_48
3V66_4/VCH
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
32
31
30
29
VDD_REF
XTAL
PLL Ref Freq
XOUT
XIN
VDD_PCI
OSC
SCLK
PLL1
I2C
Logic
VDD_48MHz
SDATA
VDD_3V66
Divider
Network
VDD_CPU
FS_[A:B]
PD#
REF0:1
VTT_PWRGD#
IREF
3V66_[0:3]
PCIF[0:2]
PCI[0:6]
DOT_48
3V66_4/VCH
2
PLL2
CPUT[0:2], CPUC[0:2]
VDD_SRC
SRCT, SRCC
USB_48
CPU_STP#
PCI_STP#
VDD_REF
DOT_48
PCI_STP#
56 SSOP/TSSOP
[1]