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PRELIMINARY
CY28341-3
Document #: 38-07580 Rev. **
Page 11 of 19
Power-down Deassertion (K7 Mode)
When deasserted PD# to high level, all clocks are enabled and
start running on the rising edge of the next full period in order
to guarantee a glitch free operation, no partial clock pulses.
PCI 33MHz
PD#
REF 14.318MHz
USB 48MHz
DDRT 133MHz
DDRC 133MHz
AGP 66MHz
CPUOD_C 133MHz
CPUCS_C 133MHz
CPUOD_T 133MHz
CPUCS_T 133MHz
Figure 4. Power-down Assertion Timing Waveform (In K7 Mode)
PC I 33M H z
PD #
CPUT 133M Hz
CPUC 133M Hz
AG P 66M H z
R EF 14.318M H z
U SB 48M H z
<1.5 m sec
DDRT 133M Hz
DDRC 133M Hz
Figure 5. Power-down Deassertion Timing Waveform (in K7 Mode)