6 / 18 page
CY28316
Document #: 38-07125 Rev. *B
Page 6 of 18
Byte 3: Control Register 3
Bit
Pin#
Name
Default
Description
Bit 7
21, 20, 18, 17
SDRAM8:11
1
(Active/Inactive).
Bit 6
–
SEL_48MHz
0
0 = 24 MHz.
1 = 48 MHz.
Bit 5
26
48MHz
1
(Active/Inactive).
Bit 4
25
24_48MHz
1
(Active/Inactive).
Bit 3
29, 28
SDRAM6:7
1
(Active/Inactive).
Bit 2
32, 31
SDRAM4:5
1
(Active/Inactive).
Bit 1
35, 34
SDRAM2:3
1
(Active/Inactive).
Bit 0
38, 37
SDRAM0:1
1
(Active/Inactive).
Byte 4: Control Register 4
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
0
Reserved.
Bit 6
–
Reserved
0
Reserved.
Bit 5
–
Reserved
0
Reserved.
Bit 4
–
Reserved
0
Reserved.
Bit 3
–
Reserved
0
Reserved.
Bit 2
–
Reserved
0
Reserved.
Bit 1
–
Reserved
0
Reserved.
Bit 0
–
Reserved
0
Reserved.
Byte 5: Control Register 5
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
0
Reserved.
Bit 6
–
Reserved
0
Reserved.
Bit 5
–
Reserved
0
Reserved.
Bit 4
–
Reserved
0
Reserved.
Bit 3
–
Reserved
0
Reserved.
Bit 2
–
Reserved
0
Reserved.
Bit 1
46
REF1
1
(Active/Inactive).
Bit 0
47
REF0
1
(Active/Inactive).
Byte 6: Watchdog Timer Register
Bit
Name
Default
Pin Description
Bit 7
PCI_Skew1
0
PCI skew control.
00 = Normal.
01 = –500 ps.
10 = Reserved.
11 = +500 ps.
Bit 6
PCI_Skew0
0
Bit 5
WD_TIMER4
1
These bits store the time-out value of the Watchdog Timer. The scale of the
timer is determined by the prescaler. The timer can support a value of 150 ms
to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec,
it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches
“0,” it will set the WD_TO_STATUS bit and generate Reset if RST_EN_WD is
enabled.
Bit 4
WD_TIMER3
1
Bit 3
WD_TIMER2
1
Bit 2
WD_TIMER1
1
Bit 1
WD_TIMER0
1
Bit 0
WD_PRE_
SCALER
0
0 = 150 ms.
1 = 2.5 sec.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
