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PacketClock™
Network Applications Clock
CY26580
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07536 Rev. *B
Revised June 03, 2004
Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• 3.3V operation
Benefits
• Internal PLL with precision operation
• Meets critical timing requirements in complex system
designs
• Enables application compatibility
Frequency Table
Part Number Outputs
Input Frequency
Output Frequencies
CY26580-1
2
125MHz or 25-MHz driven
100 MHz, 133.33 MHz
Input Select Options
SEL_25
SEL_CLK
Input Type
Input Frequency
CLK1
CLK2
Unit
X
0
Do not use
0
1
Driven
125
133.33
100
MHz
1
1
Driven
25
133.33
100
MHz
Logic Block Diagram
CLK
OUTPUT
MULTIPLEXER
AND
DIVIDERS
PLL
OSC.
133.33 MHz
Q
P
VCO
VDD
GND
Φ
GND
100 MHz
20-pin SSOP (QSOP)
1
2
3
4
5
6
7
8
14
15
16
17
18
19
20
100 MHz
GND
NC
VDD
NC
SEL_CLK
NC
NC
VDD
VDD
CY26580
Pin Configuration
9
10
NC
SEL_25
12
11
13
NC
NC
NC
NC
NC
CLK
SEL_25
SEL_CLK
NC
133 MHz
GND
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