CY26049-36
Document #: 38-07415 Rev. *C
Page 5 of 7
Voltage and Timing Definitions
Note:
3.
Dependent on crystals chosen and crystal specs.
DC Electrical Specifications (Industrial Temp: –40° to 85°C)
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
IOH
Output High Current
VOH = VDD – 0.5, VDD = 3.3V (source)
10
20
–
mA
IOL
Output Low Current
VOL = 0.5, VDD = 3.3V (sink)
10
20
–
mA
VIH
Input High Voltage
CMOS Levels
0.7
–
–
VDD
VIL
Input High Voltage
CMOS Levels
–
–
0.3
VDD
IIH
Input High Current
VIH = VDD
–5
10
µA
IIL
Input Low Current
VIL = 0V
–
5
10
µA
CIN
Input Capacitance
–
–
7
pF
IOZ
Output Leakage Current
High Z[1] output
–
± 5
–
µA
IDD
Supply Current
CLOAD = 15 pF, VDD = 3.45V, FS [3:0] = 0100
–
–
50
mA
CLOAD = 15 pF, VDD = 3.45V, FS [3:0] = 1101
–
–
35
mA
AC Electrical Specifications (Commercial Temp: 0° to 70° C and Industrial Temp: –40° to 85°C)
Parameter
Description
Test Conditions
Min.
Typ.
Max. Unit
fICLK-E
Frequency, Input Clock
Input Clock Frequency, External Mode
–
8.00
–
kHz
fICLK-B
Frequency, Input Clock
Input Clock Frequency, Buffer Mode
10
–
60
MHz
LR
FailSafe Lock Range[3]
Range of reference ICLK for Safe = High
–250
–
+250 ppm
DC = t2/t1 Output Duty Cycle
Duty Cycle defined in Figure 1, measured at 50% of VDD
45
50
55
%
TPJIT1
Clock Jitter; output > 5 MHz Period Jitter, Peak to Peak, 10,000 periods
–
–
250
ps
RMS Period Jitter, RMS
–
–
50
ps
TPJIT2
Clock Jitter; output <5 MHz Period Jitter, Peak to Peak, 10,000 periods
–
–
500
ps
RMS Period Jitter, RMS
–
–
100
ps
t6
PLL Lock Time
Time for PLL to lock within ± 150 ppm of target frequency
–
–
3
ms
tfs_lock
Failsafe Lock Time
Time for PLL to lock to ICKL (outputs phase aligned with
ICKL and Safe = High)
––
7
s
ferror
Frequency Synthesis Error
Actual mean frequency error vs. target
–
0
–
ppm
ER
Rising Edge Rate
Output Clock Edge Rate, Measured from 20% to 80% of
VDD, CLOAD = 15 pF See Figure 2.
0.8
1.4
2
V/ns
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 20% to 80% of
VDD, CLOAD = 15 pF See Figure 2.
0.8
1.4
2
V/ns
t1
t2
50%
50%
CLK
Figure 1. Duty Cycle Definition; DC = t2/t1
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
CLK
t3
t4
80%
20%
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