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CY25702
Document #: 38-07721 Rev. *C
Page 4 of 6
Application Circuit
Figure 1. Application Circuit Diagram
0.1 µ F
VDD
1
2
3
4
OE /P D #
VSS
CL K
VD D
Po w e r
C Y 257 02
Switching Waveforms
Figure 2. Duty Cycle Waveform
Figure 3. Output Rise/Fall Time Waveform
Figure 4. Output Enable/Disable Timing Waveforms
Cycle Timing (DC = t1A/t1B)
t1A
t1B
CLK
CLK
Tr
VDD
0V
Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
CLK
VDD
TOE1
VIL
VIH
OUTPUT
ENABLE
0V
(Asynchronous)
High Impedance
TOE2
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