CY25702
Document #: 38-07721 Rev. *C
Page 3 of 6
Note
1. Guaranteed by characterization, not 100% tested.
2. Jitter is configuration dependent. Actual jitter is dependent on output frequencies, spread percentage, temperature, and output load. For more information, refer
to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at http://www.cypress.com/clock/appnotes.html, or contact your
local Cypress Field Application Engineer.
DC Electrical Characteristics
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
IOH
Output High Current (pin 3)
VOH = VDD – 0.5, VDD = 3.3V (source)
10
12
–
mA
IOL
Output Low Current (pin 3)
VOL = 0.5, VDD = 3.3V (sink)
10
12
–
mA
VIH
Input High Voltage (pin 1)
CMOS levels, 70% of VDD
0.7VDD
–VDD
V
VIL
Input Low Voltage (pin 1)
CMOS levels, 30% of VDD
–
–
0.3VDD
V
IIH
Input High Current (pin 1)
Vin = VDD
––
10
μA
IIL
Input Low Current (pin 1)
Vin = VSS
––
10
μA
IOZ
Output Leakage Current (pin 3)
Three-state output, OE = 0
–10
–
10
μA
CIN
[1]
Input Capacitance (pin 1)
Pin 1, or OE
–
5
7
pF
IVDD
Supply Current
VDD = 3.3V, CLK = 1 to 166 MHz,
CLOAD = 0, OE = VDD
––
50
mA
Δf/f
Initial Accuracy at Room Temp.
TA = 25°C, 3.3V
–25
–
25
ppm
Freq. Stability over Temp. Range TA = –20°C to 70°C, 3.3V
–25
–
25
ppm
Freq. Stability over Voltage Range 3.0 to 3.6V
–12
–
12
ppm
Aging
TA = 25°C, First year
–5
–
5
ppm
AC Electrical Characteristics[1]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
CLK, Measured at VDD/2
45
50
55
%
tR
Output Rise Time
20%–80% of VDD, CL=15 pF
–
–
2.7
ns
tF
Output Fall Time
20%–80% of VDD, CL=15 pF
–
–
2.7
ns
TCCJ1
[2]
Cycle-to-Cycle Jitter CLK (Pin 3)
CLK > 133 MHz, Measured at VDD/2
–
85
200
ps
25 MHz < CLK < 133 MHz, Measured at VDD/2
–
215
400
ps
CLK < 25 MHz, Measured at VDD/2
–
–
500
ps
TOE1
Output Disable Time (pin1 = OE)
Time from falling edge on OE to stopped
outputs (Asynchronous)
–
150
350
ns
TOE2
Output Enable Time (pin1 = OE)
Time from rising edge on OE to outputs at a
valid frequency (Asynchronous)
–
150
350
ns
TLOCK
PLL Lock Time
Time for CLK to reach valid frequency
–
–
10
ms
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