CY25200
Document #: 38-07633 Rev. *D
Page 10 of 12
AC Electrical Specifications
Parameter
Description
Condition
Min
Typ.
Max
Unit
DC
Output Duty Cycle
SSCLK, Measured at VDD/2
45
50
55
%
Output Duty Cycle
REFCLK, Measured at VDD/2
Duty Cycle of CLKIN = 50%.
40
50
60
%
SR1
Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, VDD = VDDL = 3.3V
0.6
–
2.0
V/ns
SR2
Rising/Falling Edge Slew Rate SSCLK1/2/3/4
≥ 100 MHz, V
DD = VDDL = 3.3V
0.8
–
3.5
V/ns
SR3
Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, VDD = VDDL = 2.5V
0.5
–
2.2
V/ns
SR4
Rising/Falling Edge Slew Rate SSCLK1/2/3/4
≥ 100 MHz, V
DD = VDDL = 2.5V
0.6
–
3.0
V/ns
SR5
Rising/Falling Edge Slew Rate SSCLK5/6 < 100 MHz, VDD = VDDL = 3.3V
0.6
–
1.9
V/ns
SR6
Rising/Falling Edge Slew Rate SSCLK5/6
≥ 100 MHz, V
DD = VDDL = 3.3V
1.0
–
2.9
V/ns
TCCJ1
Cycle-to-Cycle Jitter
SSCLK1/2/3/4
CLKIN = SSCLK1/2/3/4 = 166MHz, ±2% spread and
SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
––
110
ps
CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
170
ps
CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
140
ps
CLKIN = SSCLK1/2/3/4 = 14.318MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
290
TCCJ2
Cycle-to-Cycle Jitter
SSCLK5/6=REFOUT
CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and
SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
100
ps
CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
120
ps
CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
180
ps
CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
180
TCCJ3
Cycle-to-Cycle Jitter
SSCLK1/2/3/4
CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and
SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
––
110
ps
CLKIN = SSCLK1/2/3/4 = 66.66MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
170
ps
CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
190
ps
CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
330
tSTP
Power Down Time
(pin3 = PD#)
Time from falling edge on PD# to stopped outputs
(Asynchronous)
–
150
300
ns
TOE1
Output Disable Time
(pin3 = OE)
Time from falling edge on OE to stopped outputs
(Asynchronous)
–
150
300
ns
TOE2
Output Enable Time
(pin3 = OE)
Time from rising edge on OE to outputs at a valid
frequency (Asynchronous)
–
150
300
ns
FMOD
Spread Spectrum Modulation
Frequency
SSCLK1/2/3/4/5/6
30.0
31.5
33.0
kHz
tPU1
Power Up Time,
Crystal is used
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous)
–3
5
ms
tPU2
Power Up Time,
Reference clock is used
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous)
–2
3
ms
tSKEW
[5]
Clock Skew
Output to output skew between related clock
outputs. Measured at VDD/2.
–
–
250
ps
[+] Feedback