DMOS Microstepping Driver with Translator

A3983

10

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Terminal List Table

Name

Number

Description

Package LP

CP1

1

Charge pump capacitor terminal

CP2

2

Charge pump capacitor terminal

VCP

3

Reservoir capacitor terminal

VREG

4

Regulator decoupling terminal

MS1

5

Logic input

MS2

6

Logic input

RESET

7

Logic input

ROSC

8

Timing set

SLEEP

9

Logic input

VDD

10

Logic supply

STEP

11

Logic input

REF

12

GND

13, 24

Ground*

DIR

14

Logic input

OUT1B

15

DMOS Full Bridge 1 Output B

VBB1

16

Load supply

SENSE1

17

Sense resistor terminal for Bridge 1

OUT1A

18

DMOS Full Bridge 1 Output A

OUT2A

19

DMOS Full Bridge 2 Output A

SENSE2

20

Sense resistor terminal for Bridge 2

VBB2

21

Load supply

OUT2B

22

DMOS Full Bridge 2 Output B

ENABLE

23

Logic input

NC

–

No connection

PAD

–

Exposed pad for enhanced thermal dissipation*

*The GND pins must be tied together externally by connecting to the PAD ground plane

under the device.

Package LP

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

CP1

CP2

VCP

VREG

MS1

MS2

RESET

ROSC

SLEEP

VDD

STEP

REF

GND

ENABLE

OUT2B

VBB2

SENSE2

GND

OUT2A

OUT1A

SENSE1

VBB1

OUT1B

DIR

PAD