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CD74HCT390 Datasheet(PDF) 1 Page - Texas Instruments |
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CD74HCT390 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 15 page 1 Data sheet acquired from Harris Semiconductor SCHS185C Features • Two BCD Decade or Bi-Quinary Counters • One Package Can Be Configured to Divide-by-2, 4, 5,10, 20, 25, 50 or 100 • Two Master Reset Inputs to Clear Each Decade Counter Individually • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Pinout CD54HCT390 (CERDIP) CD74HC390, CD74HCT390 (PDIP, SOIC) TOP VIEW Description The CD74HC390 and ’HCT390 dual 4-bit decade ripple counters are high-speed silicon-gate CMOS devices and are pin compatible with low-power Schottky TTL (LSTTL). These devices are divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide- by-5 sections. These sections are normally used in a BCD decade or bi-quinary configuration, since they share a com- mon master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCP0 and nCP1) of each section allow ripple counter or frequency divi- sion applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the High-to-Low transition of the input pulses (nCP0 and nCP1). For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide-by-5 section. For bi-quinary decade operation, the nO3 output is connected to the nCP0 input and nQ0 becomes the decade output. The master reset inputs (1MR and 2MR) are active-High asynchronous inputs to each decade counter which oper- ates on the portion of the counter identified by the “1” and “2” prefixes in the pin configuration. A High level on the nMR input overrides the clock and sets the four outputs Low. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 1CP0 1MR 1Q0 1CP1 1Q1 1Q2 GND 1Q3 VCC 2MR 2Q0 2CP1 2Q1 2Q2 2Q3 2CP0 Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HCT390F3A -55 to 125 16 Ld CERDIP CD74HC390E -55 to 125 16 Ld PDIP CD74HC390M -55 to 125 16 Ld SOIC CD74HC390MT -55 to 125 16 Ld SOIC CD74HC390M96 -55 to 125 16 Ld SOIC CD74HCT390E -55 to 125 16 Ld PDIP CD74HCT390M -55 to 125 16 Ld SOIC CD74HCT390MT -55 to 125 16 Ld SOIC CD74HCT390M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. September 1997 - Revised October 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD74HC390, CD54HCT390, CD74HCT390 High-Speed CMOS Logic Dual Decade Ripple Counter [ /Title (CD74 HC390 , CD74 HCT39 0) /Sub- ject (High Speed CMOS |
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