CY2509/10
Document #: 38-07230 Rev. *C
Page 3 of 6
Spread Aware™
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we
designed this product so as not to filter off the Spread
Spectrum feature of the Reference input, assuming it exists.
When a zero delay buffer is not designed to pass the SS
feature through, the result is a significant amount of tracking
skew which may cause problems in systems requiring
synchronization.
For more details on Spread Spectrum timing technology,
please see the Cypress application note titled, “EMI
Suppression Techniques with Spread Spectrum Frequency
Timing Generator (SSFTG) ICs.”
How to Implement Zero Delay
Typically, Zero Delay Buffers (ZDBs) are used because a
designer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this,
layout must compensate for trace length between the ZDB and
the target devices. The method of compensation is described
below.
External feedback is the trait that allows for this compensation.
Since the PLL on the ZDB will cause the feedback signal to be
in phase with the reference signal. When laying out the board,
match the trace lengths between the output being used for
feed back and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede
the input signal, this may also be affected by either making the
trace to the FBIN pin a little shorter or a little longer than the
traces to the devices being clocked.
Inserting Other Devices in Feedback Path
Another nice feature available due to the external feedback is
the ability to synchronize signals up to the signal coming from
some other device. This implementation can be applied to any
device (ASIC, multiple output clock buffer/driver, etc.) which is
put into the feedback path.
Referring to Figure 2, if the traces between the ASIC/buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin, the signals
at the destination(s) device will be driven HIGH at the same
time the Reference clock provided to the ZDB goes HIGH.
Synchronizing the other outputs of the ZDB to the outputs form
the ASIC/Buffer is more complex however, as any propagation
delay in the ASIC/Buffer must be accounted for.
3
19
20
21
22
6
5
4
7
15
16
17
18
10
9
8
13
14
12
11
1
23
24
2
GND
GND
GND
GND
AGND
FBIN
VDD
Q5
Q6
Q7
Q8
Q9
VDD
AVDD
CLK
FBOUT
OE
VDD
Q4
Q3
Q2
Q1
Q0
VDD
V
DD
VDD
0.1
µF
V
DD
V
DD
10
µF
3.3V
10
µF
FB
FB
0.1
µF
0.1
µF
0.1
µF
0.1
µF
Figure 1. Schematic
Reference
Signal
Feedback
Input
ASIC/
Buffer
Zero
Delay
Buffer
A
Figure 2. Six Output Buffers in the Feedback Path
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
