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CY5057 Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY5057
Description  High-Frequency Flash Programmable PLL Die with Spread Spectrum
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY5057 Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY5057
Document Number: 38-07363 Rev. *C
Page 5 of 10
Inkless Die Pick Map (DPM) Format
Cypress ships inkless wafers to customers with an accompa-
nying die pick map, which is used to determine the good die for
assembly and programming. Customers can also access
individual DPM files at their convenience via ftp.cypress.com
with a valid user account login and password. Contact your local
Cypress Field Application Engineer (FAE) or sales represen-
tative for a customer FTP account. The DPM files are named
using the fab lot number and wafer number scribed on the wafer.
The DPM files are transferred to the customer’s FTP account
when the factory ships out the wafers against their purchase
order (PO).
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage ................................................. –0.5 to +7.0V
Input voltage .............................................–0.5V to VDD + 0.5
Storage temperature (non condensing) ...... –55
°C to +125°C
Junction temperature................................. –40
°C to +125°C
Data retention at Tj = 125
°C..................................> 10 years
Maximum non volatile programming cycles......................100
Static discharge voltage........................................... > 2000V
(per MIL-STD-883, method 3015)
Output (pad 9) sink or sources current ........20 mA maximum
Operating Conditions
Parameter
Description
Min
Max
Unit
VDD
Supply voltage (3.3V)
3.0
3.6
V
TAJ
[2]
Operating temperature, junction
–40
100
°C
CLC
Maximum capacitive load on the output (CMOS levels spec)
VDD = 3.0V–3.6V, output frequency = 5–170 MHz
--
15
pF
XREF
Reference frequency with spread spectrum disabled. Fundamental tuned crystals only
25.1
25.1
MHz
Cin
Input capacitance (except crystal pins)
--
7
pF
CXIN
Crystal input capacitance (all internal caps off)
10
14
pF
CXout
Crystal output capacitance (all internal caps off)
10
14
pF
T_PSRT
Power up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.005
500
ms
Note
2. In Cypress standard TSSOP packages with external crystal.
[+] Feedback


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