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CY2509ZC-1 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY2509ZC-1
Description  Spread Aware?? Ten/Eleven Output Zero Delay Buffer
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2509ZC-1 Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY2509/10
Document #: 38-07230 Rev. *C
Page 4 of 6
Absolute Maximum Ratings [1]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
.
Parameter
Description
Rating
Unit
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
V
TSTG
Storage Temperature
–65 to +150
°C
TA
Operating Temperature
0 to +70
°C
TB
Ambient Temperature under Bias
–55 to +125
°C
PD
Power Dissipation
0.5
W
DC Electrical Characteristics: TA =0°C to 70°C, VDD = 3.3V ±10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
IDD
Supply Current
Unloaded, 100 MHz
200
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
2.0
VDD+0.3
V
VOL
Output Low Voltage
IOL = 12 mA
0.8
V
VOH
Output High Voltage
IOH = –12 mA
2.1
V
IIL
Input Low Current
VIN = 0V
50
µA
IIH
Input High Current
VIN = VDD
––
50
µA
AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
fOUT
Output Frequency
30-pF load[5]
40
140
MHz
tR
Output Rise Time
0.8V to 2.0V, 30-pF load
2.1
ns
tF
Output Fall Time
2.0V to 0.8V, 30-pF load
2.5
ns
tICLKR
Input Clock Rise Time[2]
––
4.5
ns
tICLKF
Input Clock Fall Time[2]
––
4.5
ns
tPEJ
CLK to FBIN Skew Variation[3, 4]
Measured at VDD/2
–350
0
350
ps
tSK
Output to Output Skew
All outputs loaded equally
–100
0
100
ps
tD
Duty Cycle
30-pF load
43
50
58
%
tLOCK
PLL Lock Time
Power supply stable
1.0
ms
tJC
Jitter, Cycle-to-Cycle
50
100
ps
Notes:
1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
2. Longer input rise and fall time will degrade skew and jitter performance.
3. Skew is measured at VDD/2 on rising edges.
4. Duty cycle is measured at VDD/2.
5. Production tests are run at 133 MHz.


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