CY2037
Document Number: 38-07354 Rev. *E
Page 4 of 11
Functional Description
CY2037
is
an
EPROM-programmable,
high
accuracy,
PLL-based die designed for the crystal oscillator market. The die
attaches directly to a low cost 10 - 30 MHz crystal and can be
packaged into a 4-pin through-hole or surface mount packages.
The oscillator devices may be stocked as blank parts and custom
frequencies programmed in-package at the last stage before
shipping. This enables fast-turn manufacture of custom and
standard crystal oscillators without the need for dedicated,
expensive crystals.
CY2037 contains an on-chip oscillator and a unique oscillator
tuning circuit for fine-tuning of the output frequency. The crystal
Cload may be selectively adjusted by programming a set of seven
EPROM bits. This feature is used to compensate for crystal
variations or to obtain a more accurate synthesized frequency.
CY2037 uses EPROM programming with a simple 2-wire, 4-pin
interface that includes VSS and VDD. Clock outputs may be
generated up to 133 MHz at 5V or up to 100 MHz at 3.3V. The
entire configuration can be reprogrammed once, which allows
the programmed inventory to be altered or reused.
CY2037 PLL die is designed for very high resolution. It has a
12-bit feedback counter multiplier and a 10-bit reference counter
divider. This enables the synthesis of highly accurate and stable
output clock frequencies with zero or low PPM error. The clock
is further modified by eight output divider options of 1, 2, 4, 8, 16,
32, 64, and 128. The divider input can be selected as the PLL or
crystal oscillator output, providing a total of 16 separate output
options. For further flexibility, the ouput is selectable between
TTL and CMOS duty cycle levels.
CY2037, CY2037B, and CY2037-2 also contain flexible power
management controls. These parts include both power down
(PD#) and OE features with integrated pull up resistors. The PD#
and OE modes have an additional setting to determine timing
(asynchronous or synchronous) with respect to the output signal.
When PD# or OE modes are enabled, CLKOUT is pulled low by
a weak pull down. The weak pull down is easily overdriven by
another active CLKOUT for applications that require multiple
CLKOUTs on a single signal path.
Controlled rise and fall times, unique output driver circuits, and
innovative circuit layout techniques enable CY2037 to have low
jitter and accurate outputs, making it suitable for most PC,
networking, and consumer applications.
On the other hand, CY2037-3 contains a frequency select
function in place of the power down and output enable modes.
For example, consumer products often require frequency
compatibility with different electrical standards around the world.
With this frequency select feature, a product that incorporates
CY2037-3 could be compatible with both NTSC for North
American, and PAL for Europe by simply changing the FS line.
The twice programmable feature is also absent in CY2037-3,
because the second EPROM row is now being used for the
alternate frequency.
EPROM Configuration Block
Table 2 summarizes the features that are configurable by
EPROM. Refer “7C8038x/7C8034X Programming Specification”
for further details. This specification can be obtained from your
Cypress factory representative.
.
PLL Output Frequency
CY2037 contains a high resolution PLL with 12-bit multiplier and
10-bit divider. The output frequency of the PLL is determined by
the following formula:
In this formula, P is the feedback counter value and Q is the
reference counter value. P and Q are EPROM programmable
values.
Power Management Features (except CY2037-3)
CY2037
contains
EPROM-programmable
PD#
and
OE
functions. If power down is selected, all active circuitry on the
chip is shut down when the control pin goes LOW. The oscillator
and PLL circuits must relock when the part leaves the power
down mode. If output enable mode is selected, the output is
tri-stated and weakly pulled low when the control pin goes low.
In this mode the oscillator and PLL circuits continue to operate,
allowing a rapid return to normal operation when the control input
is deasserted.
In addition, the PD# and OE modes can be programmed to occur
synchronously or asynchronously with respect to the output
signal. When the asynchronous setting is used, the power down
or output disable occurs immediately (allowing for logic delays),
regardless of the position in the clock cycle. However, when the
synchronous setting is used, the part waits for a falling edge at
the output before the power down or output enable signal is
initiated, thus preventing output glitches. In asynchronous or
synchronous
setting,
the
output
is
always
enabled
synchronously by waiting for the next falling edge of the output.
Table 2. EPROM Adjustable Features
Adjustable Features
Adjust
Frequency
Feedback Counter Value (P)
Reference Counter Value (Q)
Output Divider Selection
Oscillator Tuning (Load Capacitance Values)
Duty Cycle Levels (TTL or CMOS)
Power Management Mode (OE or PD#)
Power Management Timing (Synchronous or Asynchronous)
F
PLL
2P
5
+
()
•
Q2
+
()
---------------------------
F
REF
•
=
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