CY14B104N-ZS25XIT datasheet(11/22 Pages) CYPRESS

Part #	CY14B104N-ZS25XIT

Description	4-Mbit (512K x 8/256K x 16) nvSRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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11 / 22 page

PRELIMINARY

CY14B104L, CY14B104N

Document #: 001-07102 Rev. *F

Page 11 of 22

Figure 6. SRAM Read Cycle #2: CE and OE Controlled[10, 21, 23]

Figure 7. SRAM Write Cycle #1: WE Controlled[21, 22, 23]

Switching Waveforms (continued)

ADDRESS

tRC

CE

tACE

tLZCE

tPD

tHZCE

OE

tDOE

tLZOE

DATA VALID

ACTIVE

STANDBY

tPU

DQ (DATA OUT)

ICC

tLZBE

tDBE

tHZBE

HZOE

t

tHZCE

BHE , BLE

tWC

tSCE

tHA

tAW

tSA

tPWE

tSD

tHD

tHZWE

tLZWE

ADDRESS

CE

WE

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

BHE , BLE

tBW

Notes

22. CE or WE must be >VIH during address transtions.

23. BHE and BLE are applicable for x16 configuration only.

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