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CY2212
Document #: 38-07466 Rev. *A
Page 2 of 10
Crystal Requirements
These are the requirements for the recommended crystal to be
used with the CY2212 DRCG Lite clock source. The crystal
load capacitance is internally set to 11 pF.
Notes:
1. At 25°C ± 3°C.
2. CL = 10 pF.
3. –10°C to 75°C.
4. At XF ± 500 kHz.
Pin Description
Name
Pin
Description
VDDP
1
3.3V Power Supply for PLL
VSSP
2
Ground for PLL
XOUT
3
Reference Crystal Feedback
XIN
4
Reference Crystal Input
VDDL
5
1.8V Power Supply for LCLK
LCLK
6
LVCMOS Output, x1/2 Crystal Frequency
VSSL
7
Ground for LCLK
NC
8
No Connect (Reserved for Test Mode)
NC
9
No Connect (Reserved for Test Mode)
VDD
10
3.3V Power Supply
VSS
11
Ground
CLKB
12
Output Clock (complement), Connect to Rambus Channel
CLK
13
Output Clock, Connect to Rambus Channel
VSS
14
Ground
VDD
15
3.3V Power Supply
S
16
PLL Multiplier Select Input, Pull-up Resistor Internal
Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit
VDD,ABS
Max. voltage on VDD, VDDP, or VDDL with respect to ground
–0.5
4.0
V
VI, ABS
Max. voltage on any pin with respect to ground
–0.5
VDD + 0.5
V
VIL, ABS
Max. voltage on LCLK with respect to ground
–0.5
VDDL + 0.5
V
Parameter
Description
Min.
Max.
Unit
XF
Frequency
14.0625
18.75
MHz
XFTOL
Frequency Tolerance[1]
–15
15
ppm
XEQRES
Equivalent Resistance[2]
100
Ω
XTEMP
Temperature Drift[3]
10
ppm
XDRIVE
Drive Level
0.01
1500
µW
XMI
Motional Inductance
20.7
25.3
mH
XIR
Insulation Resistance
500
M
Ω
XSAR
Spurious Attenuation Ratio[4]
3dB
XOS
Overtone Spurious
8
dB
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