CY23EP09
Document #: 38-07760 Rev. *B
Page 2 of 13
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay.
The output driving the CLKOUT pin will be driving a total load
of 5 pF plus any additional load externally connected to this
pin. For applications requiring zero input-output delay, the total
load on each output pin (including CLKOUT) must be the
same. If input-output delay adjustments are required, the
CLKOUT load may be changed to vary the delay between the
REF input and remaining outputs.
For zero output-output skew, be sure to load all outputs
equally. For further information refer to the application note
entitled “CY2305 and CY2309 as PCI and SDRAM Buffers”.
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Pin Definition
Pin
Signal
Description
1REF[1]
Input reference frequency
2
CLKA1[2]
Buffered clock output, Bank A
3
CLKA2[2]
Buffered clock output, Bank A
4VDD
3.3V or 2.5V supply
5
GND
Ground
6
CLKB1[2]
Buffered clock output, Bank B
7
CLKB2[2]
Buffered clock output, Bank B
8S2[3]
Select input, bit 2
9S1[3]
Select input, bit 1
10
CLKB3[2]
Buffered clock output, Bank B
11
CLKB4[2]
Buffered clock output, Bank B
12
GND
Ground
13
VDD
3.3V or 2.5V supply
14
CLKA3[2]
Buffered clock output, Bank A
15
CLKA4[2]
Buffered clock output, Bank A
16
CLKOUT[2]
Buffered output, internal feedback on this pin
Select Input Decoding
S2
S1
CLOCK A1–A4
CLOCK B1–B4
CLKOUT[4]
Output Source
PLL Shutdown
0
0
Three-state
Three-state
Driven
PLL
N
0
1
Driven
Three-state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
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