CY22E016L
Document Number: 001-06727 Rev. *D
Page 4 of 14
If an automatic STORE on power loss is not required, then VCC
is tied to ground and +5V is applied to VCAP. This is the AutoStore
Inhibit mode where the AutoStore function is disabled. If the
CY22E016L is operated in this configuration, references to VCC
are changed to VCAP throughout this datasheet. In this mode,
STORE operations are triggered with the HSB pin. It is not
permissible to change between these three options at will.
To prevent unneeded STORE operations, automatic STOREs
and those initiated by externally driving HSB LOW are ignored,
unless at least one WRITE operation takes place since the most
recent STORE or RECALL cycle. An optional pull up resistor is
shown connected to HSB. This is used to signal the system that
the AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY22E016L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
low, the CY22E016L conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle begins if a WRITE to the
SRAM took place since the last STORE or RECALL cycle. The
HSB pin also acts as an open drain driver that is internally driven
low to indicate a busy condition, while the STORE (initiated by
any means) is in progress.
SRAM READ and WRITE operations that are in progress when
HSB is driven low by any means are given time to complete
before the STORE operation is initiated. After HSB goes low, the
CY22E016L continues SRAM operations for tDELAY. During
tDELAY, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it is allowed a time,
tDELAY, to complete. However, any SRAM WRITE cycles
requested after HSB goes LOW are inhibited until HSB returns
HIGH.
The HSB pin is used to synchronize multiple CY22E016L while
using a single larger capacitor. To operate in this mode, the HSB
pin is connected together to the HSB pins from the other
CY22E016L. An external pull up resistor to +5V is required, since
HSB acts as an open drain pull down. The VCAP pins from the
other CY22E016L parts are tied together and share a single
capacitor. The capacitor size is scaled by the number of devices
connected to it. When any one of the CY22E016L detects a
power loss and asserts HSB, the common HSB pin causes all
parts to request a STORE cycle. (A STORE takes place in those
CY22E016L that are written since the last non-volatile cycle.)
During any STORE operation, regardless of how it is initiated,
the CY22E016L continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. After completing the
STORE operation, the CY22E016L remains disabled until the
HSB pin returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC <
VSWITCH), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Data Protection
The CY22E016L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC is less than VSWITCH. If the CY22E016L is in a WRITE
mode (both CE and WE are LOW) at power up after a RECALL
or after a STORE, the WRITE is inhibited until a negative
transition on CE or WE is detected. This protects against
inadvertent writes during power up or brown out conditions.
Noise Considerations
The CY22E016L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduces circuit noise.
Low Average Active Power
CMOS technology provides the CY22E016L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 4 shows the relationship between ICC and
READ/WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY22E016L depends on the
following items:
1. The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. CMOS vs. TTL input levels
5. The operating temperature
6. The VCC level
7. IO loading
Figure 3. AutoStore Inhibit Mode
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