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Spread Aware™, Frequency Multiplier and
Zero Delay Buffer
CY23S02
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07155 Rev. *C
Revised June 7, 2005
Features
• Spread Aware™—designed to work with SSFTG
reference signals
• 90ps typical jitter OUT2
• 200ps typical jitter OUT1
• 65ps typical output-to-output skew
• 90ps typical propagation delay
• Voltage range: 3.3V±5%, or 5V±10%
• Output frequency range: 20MHz-133MHz
• Two outputs
• Configuration options allow various multiplication of
the reference frequency, refer to Table 1 to determine
the specific option which meets your multiplication
needs
• Available in 8-pin SOIC package
Table 1. Configuration Options
FBIN
FS0
FS1
OUT1
OUT2
OUT1
0
0
2 X REF
REF
OUT1
1
0
4 X REF
2 X REF
OUT1
0
1
REF
REF/2
OUT1
1
1
8 X REF
4 X REF
OUT2
0
0
4 X REF
2 X REF
OUT2
1
0
8 X REF
4 X REF
OUT2
0
1
2 X REF
REF
OUT2
1
1
16 X REF
8 X REF
Block Diagram
Pin Configuration
÷Q
FS0
FS1
Reference
FBIN
Phase
Detector
Charge
Pump
Loop
Filter
VCO
÷2
Output
Buffer
OUT1
OUT2
Output
Buffer
External feedback connection to
OUT1 or OUT2, not both
Input
IN
OUT2
VDD
OUT1
FS1
8
7
6
5
FBIN
IN
GND
FS0
1
2
3
4
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