CY23FP12-002
Document #: 38-07644 Rev. **
Page 4 of 10
Below is a list of independent functions, which can be
assigned to each of the four S1 and S2 combinations. When
a particular S1 and S2 combination is selected, the device will
assume the configuration (which is essentially a set of
functions given in Table 2, below) that has been preassigned
to that particular combination.
Inv CLKB4
Generates an inverted clock on the CLKB4 output. When this option is
programmed, CLKB4 and CLKB5 will become complimentary pairs.
Non-invert
Pull-down Enable
Enables/Disables internal pulldowns on all outputs
Enable
Fbk Pull-down Enable
Enables/Disables internal pulldowns on the feedback path (applicable to both
internal and external feedback topologies)
Enable
Fbk Sel
Selects between the internal and the external feedback topologies
Internal
Table 1. (continued)
Configuration
Description
Default
Table 2.
Function
Description
Default
Output Enable CLKB[5:4] Enables/Disables CLKB[5:4] output pair
Enable
Output Enable CLKB[3:2] Enables/Disables CLKB[3:2] output pair
Enable
Output Enable CLKB[1:0] Enables/Disables CLKB[1:0] output pair
Enable
Output Enable CLKA[5:4] Enables/Disables CLKA[5:4] output pair
Enable
Output Enable CLKA[3:2] Enables/Disables CLKA[3:2] output pair
Enable
Output Enable CLKA[1:0] Enables/Disables CLKA[1:0] output pair
Enable
Auto Power-down Enable Enables/Disables the auto power down circuit, which monitors the reference clock rising
edges and shuts down the device in case of a reference “failure.” This failure is triggered
by a drift in reference frequency below a set limit. This auto power down circuit is
disabled internally when one or more of the outputs are configured to be driven directly
from the reference clock.
Enable
PLL Power-down
Shuts down the PLL when the device is configured as a non-PLL fanout buffer.
See
Table 4
M[7:0]
Assigns an eight-bit value to reference divider –M. The divider can be any integer value
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
See
Table 4
N[7:0]
Assigns an eight-bit value to feedback divider –N. The divider can be any integer value
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
See
Table 4
X[6:0]
Assigns a seven-bit value to output divider –X. The divider can be any integer value
from 5 to 130. Divide by 1,2,3, and 4 are preprogrammed on the device and can be
activated by the appropriate output mux setting.
See
Table 4
Divider Source
Selects between the PLL output and the reference clock as the source clock for the
output dividers.
See
Table 4
CLKA54 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKA5 and CLKA4 pair. Please refer to Table 3 for a list of divider values.
See
Table 4
CLKA32 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKA3 and CLKA2 pair. Please refer to Table 3 for a list of divider values.
See
Table 4
CLKA10 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKA1 and CLKA0 pair. Please refer to Table 3 for a list of divider values.
See
Table 4
CLKB54 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKB5 and CLKB4 pair. Please refer to Table 3 for a list of divider values.
See
Table 4
CLKB32 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKB3 and CLKB2 pair. Please refer to Table 3 for a list of divider values.
See
Table 4
CLKB10 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKB1 and CLKB0 pair. Please refer to Table 3 for a list of divider values.
See
Table 4
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