CY8C42323/CY8C42423
PRELIMINARY
CY8C42123/CY8C42223
Document 38-12034 Rev. *C
Page 3 of 42
4.2
Digital System
The Digital System is composed of 4 digital PSoC blocks, 2
Enhanced Basic (Type D) and 2 Basic (Type C) to provide
unique power control pulse width modulator (PWM) features.
The power control features include integrated deadband,
latched kill, and synchronous or asynchronous kill. The kill
feature can be combined with a comparator to implement a
fast over-current protection circuit. Each block is an 8-bit
resource that can be used alone or combined with other blocks
to form 8-, 16-, 24-, and 32-bit peripherals, which are called
user module references. A sampling of digital block configura-
tions is listed below.
• PWMs (8 to 32 bit)
• PWMs with Deadband (8 to 16 bit)
• Counters (8 to 32 bit)
• Timers (8 to 32 bit)
The digital blocks can be connected to any GPIO (or digital
high voltage output) through a set of global buses that can
route any signal to any pin. The buses also allow signal multi-
plexing and the combining of signals through logic operations.
This configurability frees designs from the constraints of a
fixed peripheral controller.
4.3
Multiple Sleep Modes
The CY8C42x23 devices can have some of the system
resources (the SleepTimer/Watchdog Timer, the Voltage
Regulator or the Power Supply Supervisor) powered down in
order to achieve the desired level of sleep current. Sleep
modes with current levels from 750
µA in idle to 0.1 µA in deep
sleep, and wakeup times from instantaneous to 400
µsec are
available. Deeper sleep modes have longer wakeup times and
sleep modes with more resource power typically have shorter
wakeup times.
4.4
Analog System
The CY8C42x23 devices have solid analog performance, low
(100
µV) offsets, reduced temperature sensitivity, and are
capable of measuring 0.75% absolute voltage accuracy.
The Analog System is composed of configurable blocks to
allow creation of complex analog signal flows. Analog periph-
erals are very flexible and can be customized to support
specific application requirements. Following are some of the
more common PSoC analog functions (most available as user
modules).
• Analog-to-digital converters (up to 12-bit resolution with
single-ended or differential inputs).
• Adjustable input gain of 1/4, 1, 4, or 16 for the ADC.
• Pin-to-pin comparator with low power mode for operation
during sleep.
• Single-ended or differential comparators (up to 2) with
absolute (1.3V) reference or internal DAC reference.
• 1.3V reference (as a System Resource).
4.5
High Voltage Interface
Two types of high voltage outputs are available. HVO[0] and
HVO[1] are digital outputs that can each be configured as a
CMOS output connected between HVdd and Vss, or
configured as an open-drain drive that can be externally pulled
up to HVdd or down to Vss.
The second type, Gate Drive Outputs (GDO0 and GDO1), can
each be used to drive the gate of a high-side PFET in a linear
or switched regulator. The GDO0 and GDO1 outputs will drive
between HVdd-5V and HVdd, the signal level required for a
"logic level" PFET. The Gate Drive Outputs can be driven by
an amplifier and used to control a PFET in a linear mode. A
sense voltage can be fed back to the amplifier through an HV
attenuator to implement a constant voltage or constant current
driver. The output of the VDAC can be used to set the target
voltage of the regulator. Alternately, the Gate Drive Outputs
can be connected to the output gated PWM and used to drive
a PFET as a high-side switch in a boost or buck convertor.
Figure 4-1. Analog Block Diagram
GDO1
HVO[1]
Atten0
Atten1
AMuxBus0
AMuxBus1
AMuxBus2
AMuxBus3
P0[6]
P0[4]
P0[2]
P0[0]
P1[0]
P0[7]
P0[5]
P0[3]
P0[1]
P1[1]
ODAC0
ODAC1
VDAC0
ODAC0
VBG
IBIAS
VDAC0
VDAC1
ODAC1
VDAC1
VS1
GDO0
VS0
HVO[0]
ANALOG and HIGH VOLTAGE SECTIONS
HV Driver
DBC01
DBC00
IDAC0
COMP1
COMP0
HV Driver
Analog to
Digital
Convertor
IDAC1
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