CY22K7
Document #: 38-07333 Rev. OBS
Page 5 of 12
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• SPI Address for the CY22K7 is:
Bytes 0 to 3 will be ignored.
A6
A5
A4
A3
A2
A1
A0
R/W
1101001
−
Byte 4: Clock Control Register (1 = Active, 0 = Inactive)
Bit
Pin #
Default
Description
7
1
Active
REF0
6
24
Active
USB/IO
5
23
Active
USB0
4
20
Active
AGP1
3
19
Active
AGP0
2
42, 43
Active
CPUCLK2 (both of differential pair, “True” and “Complementary”)
1
39, 40
Active
CPUCLK1 (both of differential pair, “True” and “Complementary”)
0
36, 37
Active
CPUCLK0 (both of differential pair, “True” and “Complementary”)
Byte 5: PCI/REF Clock Control Register (1 = Active, 0 = Inactive)
Bit
Pin #
Default
Description
7
2
Active
REF1
6
17
Active
PCICLK6
5
16
Active
PCICLK5
4
14
Active
PCICLK4
3
13
Active
PCICLK3
2
11
Active
PCICLK2
1
10
Active
PCICLK1
0
8
Active
PCICLK0
Byte 6: SDRAM Clock & Generator Mode Control Register (1 = Active, 0 = Inactive)
Bit
Pin #
Default
Description
7
−
Inactive
Spread Spectrum
6
−
Active
Bits[6:4] correspond to the Function Table on page 3
Bit 6 = TEST, Bit 5 = FS1, Bit 4 = FS0
example: Bits[6:4] = ‘111’ -- 100-MHz CPUCLK and SDRAM_OUT clocks
5
−
Active
4
−
Active
3
−
Active
Reserved
2
−
Active
Reserved
1
−
Inactive
SPI (directs the generator to utilize either SPI feature selection if bit is enabled
or pin-based feature if bit is disabled)
0
46
Active
SDRAM_OUT
