CY7C1522V18
CY7C1529V18
CY7C1523V18
CY7C1524V18
Document #: 38-05564 Rev. *D
Page 6 of 28
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
Input-
Synchronous
Data Input signals, sampled on the rising edge of K and K clocks during valid Write
operations.
CY7C1522V18
− D
[7:0]
CY7C1529V18
− D
[8:0]
CY7C1523V18
− D
[17:0]
CY7C1524V18
− D
[35:0]
LD
Input-
Synchronous
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined.
This definition includes address and Read/Write direction. All transactions operate on a burst of
2 data (one period of bus activity).
NWS[1:0]
Input-
Synchronous
Nibble Write Select 0, 1
− active LOW (CY7C1522V18 only). Sampled on the rising edge of
the K and K clocks during Write operations. Used to select which nibble is written into the device
during the current portion of the Write operations. Nibbles not written remain unaltered.
NWS0 controls D[8:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
BWS
[3:0]
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3
− active LOW. Sampled on the rising edge of the K and K
clocks during Write operations. Used to select which byte is written into the device during the
current portion of the Write operations. Bytes not written remain unaltered.
CY7C1522V18
− BWS
0 controls D[3:0] and BWS1 controls D[7:4].
CY7C1523V18
− BWS
0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1524V18
− BWS
0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27]
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active Read and Write
operations. These address inputs are multiplexed for both Read and Write operations. Internally,
the device is organized as 8M x 8 (2 arrays each of 4M x 8) for CY7C1522V18, 8M x 9 (2 arrays
each of 4M x 8) for CY7C1529V18,4M x 18 (two arrays each of 2Mx 18) for CY7C1523V18 and
2M x 36 (2 arrays each of 1M x 36) for CY7C1524V18. Therefore only 22 address inputs are
needed to access the entire memory array of CY7C1522V18 and CY7C1529V18, 21 address
inputs for CY7C1523V18, and 20 address inputs for CY7C1524V18. These inputs are ignored
when the appropriate port is deselected.
Q[x:0]
Output-
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C clocks during Read operations or K
and K when in single clock mode. When Read access is deselected, Q[x:0] are automatically
tri-stated.
CY7C1522V18
− Q
[7:0]
CY7C1523V18
− Q
[17:0]
CY7C1524V18
− Q
[35:0]
R/W
Input-
Synchronous
Synchronous Read/Write Input: When LD is LOW, this input designates the access type (Read
when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up
and hold times around edge of K.
C
Input-
Clock
Positive input clock for output data . C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
C
Input-
Clock
Negative input clock for output data . C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
K
Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.