CY7C66013C, CY7C66113C
Document Number: 38-08024 Rev. *C
Page 2 of 58
Clock
The microcontroller uses an external 6 MHz crystal and an
internal oscillator to provide a reference to an internal PLL based
clock generator. This technology allows the customer application
to use an inexpensive 6 MHz fundamental crystal that reduces
the clock related noise emissions (EMI). A PLL clock generator
provides the 6, 12, and 48 MHz clock signals for distribution
within the microcontroller.
Memory
The CY7C66013C and CY7C66113C have 8 KB of PROM.
Power-on Reset, Watchdog, and Free-running Timer
These parts include POR logic, a WDT, and a 12-bit free-running
timer. The POR logic detects when power is applied to the
device, resets the logic to a known state, and begins executing
instructions at PROM address 0x0000. The WDT is used to
ensure that the microcontroller recovers after a period of
inactivity. The firmware may become inactive for a variety of
reasons, including errors in the code or a hardware failure such
as waiting for an interrupt that never occurs.
I2C and HAPI Interface
The microcontroller communicates with external electronics
through the GPIO pins. An I2C compatible interface accommo-
dates a 100 kHz serial link with an external device. There is also
a Hardware assisted Parallel Interface (HAPI) to transfer data to
an external device.
Timer
The free-running 12-bit timer clocked at 1 MHz provides two
interrupt sources, 128
μs and 1.024 ms. The timer is used to
measure the duration of an event under firmware control by
reading the timer at the start of the event and after the event is
complete. The difference between the two readings indicates the
duration of the event in microseconds. The upper four bits of the
timer are latched into an internal register when the firmware
reads the lower eight bits. A read from the upper four bits actually
reads data from the internal register, instead of the timer. This
feature eliminates the need for firmware to try to compensate if
the upper four bits increment immediately after the lower eight
bits are read.
Interrupts
The microcontroller supports eleven maskable interrupts in the
vectored interrupt controller. Interrupt sources include the 128
μs
(bit 6) and 1.024 ms (bit 9) outputs from the free-running timer,
five USB endpoints, the USB hub, the DAC port, the GPIO ports,
and the I2C compatible master mode interface. The timer bits
cause an interrupt (if enabled) when the bit toggles from LOW ‘0’
to HIGH ‘1.’ The USB endpoints interrupt after the USB host has
written data to the endpoint FIFO or after the USB controller
sends a packet to the USB host. The DAC ports have an
additional level of masking that allows the user to select which
DAC inputs causes a DAC interrupt. The GPIO ports also have
a level of masking to select which GPIO inputs causes a GPIO
interrupt. For additional flexibility, the input transition polarity that
causes an interrupt is programmable for each pin of the DAC
port. Input transition polarity is programmed for each GPIO port
as part of the port configuration. The interrupt polarity can be
rising edge (‘0’ to ‘1’) or falling edge (‘1’ to ‘0’).
USB
The CY7C66013C and CY7C66113C include an integrated USB
Serial Interface Engine (SIE) that supports the integrated periph-
erals and the hub controller function. The hardware supports up
to two USB device addresses with one device address for the
hub (two endpoints) and a device address for a compound
device (three endpoints). The SIE allows the USB host to
communicate with the hub and functions integrated into the
microcontroller. The part includes a 1:4 hub repeater with one
upstream port and four downstream ports. The USB Hub allows
power-management control of the downstream ports by using
GPIO pins assigned by the user firmware. The user has the
option of ganging the downstream ports together with a single
pair
of
power
management
pins,
or
providing
power
management for each port with four pairs of power management
pins.
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