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Part Name  Description 
CD54HC4059_08 Datasheet(PDF) 1 Page  Texas Instruments 


1 page 1 Data sheet acquired from Harris Semiconductor SCHS206B Features • Synchronous Programmable ÷N Counter N = 3 to 9999 or 15999 • Presettable DownCounter • Fully Static Operation • ModeSelect Control of Initial Decade Counting Function ( ÷10, 8, 5, 4, 2) • Master Preset Initialization • Latchable ÷N Output • Fanout (Over Temperature Range)  Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads  Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . 55oC to 125oC • Balanced Propagation Delay and Transition Times • Signiﬁcant Power Reduction Compared to LSTTL Logic ICs • HC Types  2V to 6V Operation  High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V Applications • Communications Digital Frequency Synthesizers; VHF, UHF, FM, AM, etc. • Fixed or Programmable Frequency Division • “Time Out” Timer for ConsumerApplication Industrial Controls Description The ’HC4059 are highspeed silicongate devices that are pincompatible with the CD4059A devices of the CD4000B series. These devices are dividebyN downcounters that can be programmed to divide an input frequency by any number “N” from 3 to 15,999. The output signal is a pulse one clock cycle wide occurring at a rate equal to the input frequency divide by N. The downcounter is preset by means of 16 jam inputs. The three ModeSelect Inputs Ka,Kb and Kc determine the modulus (“divideby” number) of the first and last counting sections in accordance with the truth table. Every time the first (fastest) counting section goes through one cycle, it reduces by 1 the number that has been preset (jammed) into the three decades of the intermediate counting section an the last counting section, which consists of flipflops that are not needed for opening the first counting section. For example, in the ÷2 mode, only one flipflop is needed in the first counting section. Therefore the last counting section has three flipflops that can be preset to a maximum count of seven with a place value of thousands. If ÷10 is desired for the first section, Ka is set “high”, Kb “high” and Kc “low”. Jam inputs J1, J2, J3, and J4 are used to preset the first counting section and there is no last counting section. The intermediate counting section consists of three cascaded BCD decade ( ÷10) counters presettable by means of Jam Inputs J5 through J16. The ModeSelect Inputs permit frequencysynthesizer channel separations of 10, 12.5, 20, 25 or 50 parts. These inputs set the maximum value of N at 9999 (when the ﬁrst counting section divides by 5 or 10) or 15,999 (when the ﬁrst counting section divides by 8, 4, or 2). The three decades of the intermediate counter can be preset to a binary 15 instead of a binary 9, while their place values are still 1, 10, and 100, multiplied by the number of the ÷N mode. For example, in the ÷8 mode, the number from which counting down begins can be preset to: 3rd Decade 1500 2nd Decade 150 1st Decade 15 Last Counting Section 1000 The total of these numbers (2665) times 8 equals 12,320. The ﬁrst counting section can be preset to 7. Therefore, 21,327 is the maximum possible count in the ÷8 mode. The highest count of the various modes is shown in the Extended Counter Range column. Control inputs Kb and Kc can be used to initiate and lock the counter in the “master preset” state. In this condition the flipflops in the counter are preset in accordance with the jam inputs and the counter remains in that state as long as Kb and Kc both remain low. The counter begins to count down from the preset state when a counting mode other than the master preset mode is selected. Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC4059F3A 55 to 125 24 Ld CERDIP CD74HC4059E 55 to 125 24 Ld PDIP CD74HC4059M96 55 to 125 24 Ld SOIC NOTE: When ordering, use the entire part number. The sufﬁx 96 denotes tape and reel. February 1998  Revised May 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD54HC4059, CD74HC4059 HighSpeed CMOS Logic CMOS Programmable DividebyN Counter [ /Title (CD74 HC4059 ) /Sub ject (High Speed CMOS Logic CMOS Pro 
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