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CY7C65113C-SXCT Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY7C65113C-SXCT
Description  USB Hub with Microcontroller
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C65113C-SXCT Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C65113C
Document #: 38-08002 Rev. *D
Page 3 of 49
16.0 USB HUB .....................................................................................................................................29
16.1 Connecting/Disconnecting a USB Device ..............................................................................29
16.2 Enabling/Disabling a USB Device ..........................................................................................30
16.3 Hub Downstream Ports Status and Control ...........................................................................30
16.4 Downstream Port Suspend and Resume ...............................................................................32
16.5 USB Upstream Port Status and Control .................................................................................33
17.0 USB SERIAL INTERFACE ENGINE OPERATION .....................................................................34
17.1 USB Device Addresses ..........................................................................................................34
17.2 USB Device Endpoints ...........................................................................................................34
17.3 USB Control Endpoint Mode Registers ..................................................................................35
17.4 USB Non-control Endpoint Mode Registers ...........................................................................36
17.5 USB Endpoint Counter Registers ...........................................................................................36
17.6 Endpoint Mode/Count Registers Update and Locking Mechanism ........................................37
18.0 USB MODE TABLES ..................................................................................................................39
19.0 REGISTER SUMMARY ...............................................................................................................43
20.0 SAMPLE SCHEMATIC ................................................................................................................45
21.0 ABSOLUTE MAXIMUM RATINGS ..............................................................................................45
22.0 ELECTRICAL CHARACTERISTICS ...........................................................................................46
23.0 SWITCHING CHARACTERISTICS ..............................................................................................47
24.0 ORDERING INFORMATION .......................................................................................................48
25.0 PACKAGE DIAGRAM .................................................................................................................48
LIST OF FIGURES
Figure 5-1. Program Memory Space with Interrupt Vector Table .........................................................12
Figure 6-1. Clock Oscillator On-Chip Circuit ........................................................................................15
Figure 7-1. Watchdog Reset (Address 0x26) .......................................................................................16
Figure 9-1. Block Diagram of a GPIO Pin ............................................................................................17
Figure 9-2. Port 0 Data ........................................................................................................................17
Figure 9-3. Port1 Data .........................................................................................................................17
Figure 9-4. GPIO Configuration Register .............................................................................................18
Figure 9-5. Port 0 Interrupt Enable .......................................................................................................19
Figure 9-6. Port 1 Interrupt Enable .......................................................................................................19
Figure 10-1. Timer LSB Register .........................................................................................................20
Figure 10-2. Timer MSB Register ........................................................................................................20
Figure 10-3. Timer Block Diagram .......................................................................................................20
Figure 11-1. I2C Configuration Register ...............................................................................................20
Figure 12-1. I2C Data Register .............................................................................................................21
Figure 12-2. I2C Status and Control Register .......................................................................................21
Figure 13-1. Processor Status and Control Register ...........................................................................23
Figure 14-1. Global Interrupt Enable Register .....................................................................................24
Figure 14-2. USB Endpoint Interrupt Enable Register .........................................................................24
Figure 14-3. Interrupt Controller Function Diagram .............................................................................25
Figure 14-4. GPIO Interrupt Structure ..................................................................................................27
Figure 16-1. Hub Ports Connect Status ...............................................................................................29
Figure 16-2. Hub Ports Speed .............................................................................................................30
Figure 16-3. Hub Ports Enable Register ..............................................................................................30
Figure 16-4. Hub Downstream Ports Control Register .........................................................................31


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