10 / 19 page
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Document #: 38-06016 Rev. *C
Page 10 of 19
Reset Timing[17]
First Data Word Latency after Reset with Simultaneous Read and Write
Notes:
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
19. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
20. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or
tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).
21. The first word is available the cycle after EF goes HIGH, always.
Switching Waveforms (continued)
tRS
tRSR
Q0- Q8
RS
tRSF
tRSF
tRSF
OE = 1
OE = 0
REN1,
REN2
EF,PAE
FF,PAF,
tRSS
tRSR
tRSS
tRSR
tRSS
WEN2/LD
WEN1
[18]
[19]
D0(FIRSTVALIDWrite)
tSKEW1
WEN1
WCLK
Q0 –Q8
EF
REN1,
REN2
OE
tOE
tENS
tOLZ
tDS
RCLK
tREF
tA
tFRL
D1
D2
D3
D4
D0
D1
D0–D8
tA
WEN2
(if applicable)
[20]
[21]
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