16K/32K x 9 Deep Sync FIFOs
CY7C4261
CY7C4271
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-06015 Rev. *C
Revised August 2, 2005
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 16K × 9 (CY7C4261)
• 32K × 9 (CY7C4271)
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power — ICC = 35 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL-compatible
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Military temp SMD Offering – CY7C4271-15LMB
• 32-pin PLCC/LCC and 32-pin TQFP
• Pin-compatible density upgrade to CY7C42X1 family
• Pin-compatible density upgrade to
IDT72201/11/21/31/41/51
• Pb-Free Packages Available
Functional Description
The CY7C4261/71 are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can
be cascaded to increase FIFO width. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the CY7C4261/71
has an output enable pin (OE). The read (RCLK) and write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable. Depth expansion is possible using one enable
input for system control, while the other enable is controlled by
expansion logic to direct the flow of data.
Logic Block Diagram
Pin Configuration
THREE-STATE
OUTPUT REGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D0–8
RCLK
EF
PAE
PAF
Q0–8
WEN1
WCLK
RS
OE
RAM
ARRAY
16K x 9
32K x 9
WEN2/LD
REN1 REN2
FF
PLCC/LCC
D1
D0
RCLK
VCC
GND
WCLK
WEN2/LD
Q8
Q7
PAF
PAE
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
REN1
OE
REN2
43 21
31 30
32
D1
D0
RCLK
GND
PAF
PAE
REN1
REN2
21
22
23
24
27
28
29
25
26
14 15 16 17 18 19 20
17
18
19
20
21
22
23
24
14 15 16
910 11 12 13
31 30
32
29 28 27
25
26
Q6
Q5
WEN1
RS
VCC
WCLK
WEN2/LD
Q8
Q7
Q6
Q5
WEN1
TQFP
Top View
Top View
CY7C4261
CY7C4271
CY7C4261
CY7C4271
16K/32K x 9 Deep Sync FIFOsCY7C4271CY7C4261
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