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CY7C09159AV
CY7C09169AV
Document #: 38-06053 Rev. *B
Page 9 of 16
Pipelined Read-to-Write-to-Read (OE = VIL)[10, 17, 18, 19]
Pipelined Read-to-Write-to-Read (OE Controlled)[10, 17, 18, 19]
Notes:
17. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
18. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
19. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Switching Waveforms (continued)
tCYC2
tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
tHW
tSW
tCD2
tCKHZ
tSD tHD
tCKLZ
tCD2
NO OPERATION
WRITE
READ
READ
CLK
CE0
CE1
R/W
ADDRESS
DATAIN
DATAOUT
An
An+1
An+2
An+2
Dn+2
An+3
An+4
Qn
Qn+3
tCYC2
tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
An
An+1
An+2
An+3
An+4
An+5
tHW
tSW
tSD tHD
Dn+2
tCD2
tOHZ
READ
READ
WRITE
Dn+3
tCKLZ
tCD2
Qn
Qn+4
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
DATAIN
OE
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