CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
Document #: 38-06029 Rev. *C
Page 3 of 20
Selection Guide
CY7C42X5V-15
CY7C42X5V-25
CY7C42X5V-35
Unit
Maximum Frequency
66.7
40
28.6
MHz
Maximum Access Time
11
15
20
ns
Minimum Cycle Time
15
25
35
ns
Minimum Data or Enable Set-up
4
6
7
ns
Minimum Data or Enable Hold
1
1
2
ns
Maximum Flag Delay
11
15
20
ns
Operating Current
Commercial
30
30
30
mA
CY7C4425V
CY7C4205V
CY7C4215V
CY7C4225V
CY7C4235V
CY7C4245V
Density
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
Packages
64-pin 14x14
TQFP
64-pin 10x10
STQFP
64-pin 14x14
TQFP
64-pin 10x10
STQFP
64-pin 14x14
TQFP
64-pin 10x10
STQFP
64-pin 14x14
TQFP
64-pin 10x10
STQFP
64-pin 14x14
TQFP
64-pin 10x10
STQFP
64-pin 14x14
TQFP
64-pin 10x10
STQFP
Pin Definitions
Signal Name
Description
I/O
Function
D0−17
Data Inputs
I
Data inputs for an 18-bit bus.
Q0−17
Data Outputs
O Data outputs for an 18-bit bus.
WEN
Write Enable
I
Enables the WCLK input.
REN
Read Enable
I
Enables the RCLK input.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is
not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is
not Empty. When LD is asserted, RCLK reads data out of the programmable
flag-offset register.
WXO/HF
Write Expansion
Out/Half Full Flag
O Dual-Mode Pin. Single device or width expansion - Half Full status flag. Cascaded –
Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O When PAE is LOW, the FIFO is almost empty based on the almost empty
offset value programmed into the FIFO. PAE is asynchronous when
VCC/SMODE is tied to VCC; it is synchronized to RCLK when VCC/SMODE is tied
to VSS.
PAF
Programmable
Almost Full
O When PAF is LOW, the FIFO is almost full based on the almost full offset
value programmed into the FIFO. PAF is asynchronous when VCC/SMODE is
tied to VCC; it is synchronized to WCLK when VCC/SMODE is tied to VSS.
LD
Load
I
When LD is LOW, D0−17 (O0−17) are written (read) into (from) the program-
mable-flag-offset register.
FL/RT
First Load/
Retransmit
I
Dual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to
VSS; all other devices will have FL tied to VCC. In standard mode of width
expansion, FL is tied to VSS on all devices. Not Cascaded – Tied to VSS. Retransmit
function is also available in standalone mode by strobing RT.
WXI
Write Expansion
Input
I
Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to VSS.
RXI
Read Expansion
Input
I
Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to VSS.
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