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CY7C4281
CY7C4291
Document #: 38-06007 Rev. *C
Page 9 of 16
Reset Timing[15]
Notes:
15. The clocks (RCLK, WCLK) can be free-running during reset.
16. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
17. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
Switching Waveforms (continued)
tRS
tRSR
RS
tRSF
tRSF
tRSF
OE = 1
OE = 0
REN1,
REN2
EF,PAE
FF,PAF
tRSS
tRSR
tRSS
tRSR
tRSS
WEN2/LD
WEN1
[17]
[16]
Q0–Q8
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