CY7C1522V18
CY7C1529V18
CY7C1523V18
CY7C1524V18
Document #: 38-05564 Rev. *D
Page 7 of 28
CQ
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized to the
Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the
Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF
Input
DLL Turn Off, active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
TDO
Output
TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
VSS/144M
Input
Address expansion for 144M. Can be tied to any voltage level.
VSS/288M
Input
Address expansion for 288M. Can be tied to any voltage level.
VREF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
Outputs as well as AC measurement points.
VDD
Power Supply
Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
Power Supply
Power supply inputs for the outputs of the device.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
Pin Definitions (continued)
Pin Name
I/O
Pin Description
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