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CY7C1517V18
CY7C1528V18
CY7C1519V18
CY7C1521V18
Document #: 38-05565 Rev. *E
Page 3 of 28
Logic Block Diagram (CY7C1519V18)
4M x 18 Array
CLK
A(21:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[17:0]
Output
Logic
Reg.
Reg.
Reg.
36
18
72
18
BWS[1:0]
VREF
Write
Reg
36
22
C
C
Write
Reg
Write
Reg
Write
Reg
18
LD
Control
Burst
Logic
A(1:0)
A(21:2)
20
CQ
CQ
2
R/W
DOFF
Logic Block Diagram (CY7C1521V18)
2M x 36 Array
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[35:0]
Output
Logic
Reg.
Reg.
Reg.
72
36
144
36
BWS[3:0]
VREF
Write
Reg
72
21
C
C
Write
Reg
Write
Reg
Write
Reg
36
LD
Control
Burst
Logic
A(1:0)
A(20:2)
19
CQ
CQ
2
R/W
DOFF