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CY7C4425V-25ASC Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY7C4425V-25ASC
Description  64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C4425V-25ASC Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
Document #: 38-06029 Rev. *C
Page 6 of 20
Width Expansion Configuration
The CY7C42X5V can be expanded in width to provide word
widths greater than 18 in increments of 18. During width
expansion mode all control line inputs are common and all
flags are available. Empty (Full) flags should be created by
ANDing the Empty (Full) flags of every FIFO. This technique
will avoid ready data from the FIFO that is “staggered” by one
clock cycle due to the variations in skew between RCLK and
WCLK. Figure 2 demonstrates a 36-word width by using two
CY7C42X5V.
Depth Expansion Configuration (with Program-
mable Flags)
The CY7C42X5V can easily be adapted to applications
requiring more than 64/256/512/1024/2048/4096 words of
buffering. Figure 2 shows Depth Expansion using three
CY7C42X5Vs. Maximum depth is limited only by signal
loading. Follow these steps:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must
be tied to the Write Expansion In (WXI) pin of the next
device.
4. The Read Expansion Out (RXO) pin of each device must
be tied to the Read Expansion In (RXI) pin of the next
device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth
Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
Figure 1. Block Diagram of Low-Voltage Synchronous FIFO Memories Used in a Width Expansion Configuration
FF
FF
EF
EF
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
FULL FLAG (FF)
7C4425V
7C4205V
7C4215V
7C4225V
7C4235V
7C4245V
7C4425V
7C4205V
7C4215V
7C4225V
7C4235V
7C4245V
18
36
DATAIN (D)
RESET(RS)
18
RESET (RS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE(OE)
PROGRAMMABLE(PAF)
EMPTYFLAG (EF)
18
DATA OUT (Q)
18
36
FIRSTLOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)


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