CY7C1441AV25
CY7C1443AV25
CY7C1447AV25
Document #: 38-05349 Rev. *F
Page 9 of 31
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQS will be written
into the specified address location. Byte writes are allowed. All
I/Os are tri-stated when a write is detected, even a byte write.
Since this is a common I/O device, the asynchronous OE input
signal must be deasserted and the I/Os must be tri-stated prior
to the presentation of data to DQs. As a safety precaution, the
data lines are tri-stated once a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1441AV25/CY7C1443AV25/CY7C1447AV25
provides an on-chip two-bit wraparound burst counter inside
the SRAM. The burst counter is fed by A[1:0], and can follow
either a linear or interleaved burst order. The burst order is
determined by the state of the MODE input. A LOW on MODE
will select a linear burst sequence. A HIGH on MODE will
select an interleaved burst order. Leaving MODE unconnected
will cause the device to default to a interleaved burst
sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW..
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
100
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
tZZI
ZZ active to sleep current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
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