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PRELIMINARY
CY7C1399D
Document #: 38-05467 Rev. *C
Page 5 of 10
tHZCE
CE HIGH to High Z[8, 9]
56
7
ns
tPU
CE LOW to Power-Up
0
0
0
ns
tPD
CE HIGH to Power-Down
10
12
15
ns
Write Cycle[10, 11]
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
8
8
10
ns
tAW
Address Set-Up to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
ns
tSD
Data Set-Up to Write End
5
7
8
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
WE LOW to High Z[10]
77
7
ns
tLZWE
WE HIGH to Low Z[8]
33
3
ns
Notes:
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±200 mV from steady state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Switching Characteristics Over the Operating Range (continued)[7]
Parameter
Description
1399D-10
1399D-12
1399D-15
Min.
Max.
Min.
Max.
Min.
Max.
Unit