Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C1387CV25-250AC Datasheet(PDF) 11 Page - Cypress Semiconductor

Part # CY7C1387CV25-250AC
Description  18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
Download  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1387CV25-250AC Datasheet(HTML) 11 Page - Cypress Semiconductor

Back Button CY7C1387CV25-250AC Datasheet HTML 7Page - Cypress Semiconductor CY7C1387CV25-250AC Datasheet HTML 8Page - Cypress Semiconductor CY7C1387CV25-250AC Datasheet HTML 9Page - Cypress Semiconductor CY7C1387CV25-250AC Datasheet HTML 10Page - Cypress Semiconductor CY7C1387CV25-250AC Datasheet HTML 11Page - Cypress Semiconductor CY7C1387CV25-250AC Datasheet HTML 12Page - Cypress Semiconductor CY7C1387CV25-250AC Datasheet HTML 13Page - Cypress Semiconductor CY7C1387CV25-250AC Datasheet HTML 14Page - Cypress Semiconductor CY7C1387CV25-250AC Datasheet HTML 15Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 36 page
background image
CY7C1386CV25
CY7C1387CV25
Document #: 38-05242 Rev. *A
Page 11 of 36
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1386CV25/CY7C1387CV25 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486
 processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Synchronous Chip Selects CE1, CE2, CE3[2] and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tco if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE signal. Consecutive single
read cycles are supported.
The CY7C1386CV25/CY7C1387CV25 is a double-cycle
deselect part. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will tri-state immediately after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and BWX) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the memory core. If GW is HIGH,
then the write operation is controlled by BWE and BWX
signals. The CY7C1386CV25/CY7C1387CV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Because the CY7C1386CV25/CY7C1387CV25 is a common
I/O device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQ are automati-
cally tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BWX) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
being delivered to the memory core. The ADV input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQX is written into the corresponding address
location in the memory core. If a byte write is conducted, only
the selected bytes are written. Bytes not selected during a byte
write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because the CY7C1386CV25/CY7C1387CV25 is a common
I/O device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQX inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQX are automati-
cally tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Burst Sequences
The CY7C1386CV25/CY7C1387CV25 provides a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel® Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input. Both
read and write burst operations are supported.


Similar Part No. - CY7C1387CV25-250AC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1387C CYPRESS-CY7C1387C Datasheet
554Kb / 34P
   18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387C-167AC CYPRESS-CY7C1387C-167AC Datasheet
554Kb / 34P
   18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387C-167AI CYPRESS-CY7C1387C-167AI Datasheet
554Kb / 34P
   18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387C-167BGC CYPRESS-CY7C1387C-167BGC Datasheet
554Kb / 34P
   18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387C-167BGI CYPRESS-CY7C1387C-167BGI Datasheet
554Kb / 34P
   18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
More results

Similar Description - CY7C1387CV25-250AC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1386C CYPRESS-CY7C1386C Datasheet
554Kb / 34P
   18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386DV25 CYPRESS-CY7C1386DV25 Datasheet
1Mb / 30P
   18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386B CYPRESS-CY7C1386B Datasheet
789Kb / 32P
   512K x 36/1M x 18 Pipelined DCD SRAM
CY7C1366B CYPRESS-CY7C1366B Datasheet
550Kb / 32P
   9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1380C CYPRESS-CY7C1380C Datasheet
788Kb / 36P
   18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1386D CYPRESS-CY7C1386D_07 Datasheet
1Mb / 30P
   18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387D CYPRESS-CY7C1387D Datasheet
481Kb / 29P
   18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1444AV25 CYPRESS-CY7C1444AV25 Datasheet
440Kb / 26P
   36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM
CY7C1444AV33 CYPRESS-CY7C1444AV33 Datasheet
479Kb / 26P
   36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1380CV25 CYPRESS-CY7C1380CV25 Datasheet
519Kb / 33P
   512K x 36/1M x 18 Pipelined SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com