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CY7C1311CV18, CY7C1911CV18
CY7C1313CV18, CY7C1315CV18
Document Number: 001-07165 Rev. *C
Page 2 of 31
Logic Block Diagram (CY7C1311CV18)
Logic Block Diagram (CY7C1911CV18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
19
32
8
NWS[1:0]
VREF
Write
Reg
16
A(18:0)
19
8
CQ
CQ
DOFF
Q[7:0]
8
8
8
8
Write
Reg
Write
Reg
Write
Reg
C
C
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
19
36
9
BWS[0]
VREF
Write
Reg
18
A(18:0)
19
9
CQ
CQ
DOFF
Q[8:0]
9
9
9
9
Write
Reg
Write
Reg
Write
Reg
C
C
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