6 / 28 page  CY7C1354A CY7C1356A Document #: 38-05161Rev. *E Page 6 of 28 51, 52, 53, 56-59, 62, 63 68, 69, 72-75, 78, 79, 80 1, 2, 3, 6-9, 12, 13 18, 19, 22-25, 28, 29, 30 (a) 6P, 7P, 7N, 6N, 6M, 6L, 7L, 6K, 7K, (b) 7H, 6H, 7G, 6G, 6F, 6E, 7E, 7D, 6D, (c) 2D, 1D, 1E, 2E, 2F, 1G, 2G, 1H, 2H, (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P DQa DQb DQc DQd Input/ Output Data Inputs/Outputs: Both the data input path and data output path are registered and triggered by the rising edge of CLK. Byte “a” is DQa pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins. 38 39 43 2U 3U 4U TMS TDI TCK Input IEEE 1149.1 Test Inputs: LVTTL-level inputs. If Serial Boundary Scan (JTAG) is not used, these pins can be floating (i.e., No Connect) or be connected to VCC. 42 5U TDO Output IEEE 1149.1 Test Output: LVTTL-level output. If Serial Boundary Scan (JTAG) is not used, these pins can be floating (i.e., No Connect). 14, 15, 16, 41, 65, 66, 91 4C, 2J, 4J, 6J, 4R, 5R VCC Supply Power Supply: +3.3V –5% and +5%. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P VSS Ground Ground: GND. 4, 11, 20, 27, 54, 61, 70, 77 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VCCQ I/O Supply Output Buffer Supply: +3.3V –0.165V and +0.165V for 3.3V I/O. +2.5V –0.125V and +0.4V for 2.5V I/O. 84 4A, 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 7R, 1T, 2T, 6T, 6U NC – No Connect: These signals are not internally connected. It can be left floating or be connected to VCC or to GND. Pin Descriptions—256K × 36 (continued) 256K × 36 TQFP Pins 256K × 36 PBGA Pins Pin Name Type Pin Description Pin Descriptions—512K × 18 512K × 18 TQFP Pins 512K × 18 PBGA Pins Pin Name Type Pin Description 37, 36, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 83, 99, 100 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 4G, 2R, 6R, 2T, 3T, 5T, 6T A0, A1, A Input- Synchronous Synchronous Address Inputs: The address register is triggered by a combination of the rising edge of CLK, ADV/LD LOW, CEN LOW, and true chip enables. A0 and A1 are the two least significant bits of the address field and set the internal burst counter if burst cycle is initiated. 93, 94, 5L 3G BWa, BWb Input- Synchronous Synchronous Byte Write Enables: Each nine-bit byte has its own active LOW byte Write enable. On load Write cycles (when WEN and ADV/LD are sampled LOW), the appropriate byte Write signal (BWx) must be valid. The byte Write signal must also be valid on each cycle of a burst Write. Byte Write signals are ignored when WEN is sampled HIGH. The appropriate byte(s) of data are written into the device two cycles later. BWa controls DQa pins; BWb controls DQb pins. BWx can all be tied LOW if always doing Write to the entire 18-bit word. 87 4M CEN Input- Synchronous Synchronous Clock Enable Input: When CEN is sampled HIGH, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled HIGH on the device outputs is as if the LOW-to-HIGH clock transition did not occur. For normal operation, CEN must be sampled LOW at rising edge of clock. |
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