CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Document Number: 38-05622 Rev. *C
Page 9 of 28
Application Example[1]
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
DQ
DQ
DQ
DQ
Write Cycle:
Load address; wait one
cycle; input write data on
four consecutive K and K
rising edges.
L-H
L
L
D(A1) at K(t + 1)
↑ D(A2) at K(t + 1) ↑ D(A3) at K(t + 2) ↑ D(A4) at K(t + 2) ↑
Read Cycle:
Load address; wait one
and a half cycle; read
data on four consecutive
C and C rising edges.
L-H
L
H
Q(A1) at C(t + 1)
↑ Q(A2) at C(t + 2) ↑ Q(A3) at C(t + 2) ↑ Q(A4) at C(t + 3) ↑
NOP: No Operation
L-H
H
X
High-Z
High-Z
High-Z
High-Z
Standby: Clock Stopped Stopped X
X
Previous State
Previous State
Previous State
Previous State
Linear Burst Address Table (CY7C1319BV18 and CY7C1321BV18)
First Address (External)
Second Address (Internal)
Third Address (Internal)
Fourth Address (Internal)
X..X00
X..X01
X..X10
X..X11
X..X01
X..X10
X..X11
X..X00
X..X10
X..X11
X..X00
X..X01
X..X11
X..X00
X..X01
X..X10
Notes:
1. The above application shows 2 DDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
↑ represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. On CY7C1319BV18 and CY7C1321BV18, “A1” represents address location latched by the devices when transaction was initiated and A2, A3, A4 represents
the addresses sequence in the burst. On CY7C1317BV18, “A1” represents A + ‘00’, A2 represents A + ‘01’, “A3” represents A + ‘10’ and “A4” represents A + ‘11’.
5. “t” represents the cycle at which a Read/Write operation is started. t+1, t + 2 and t +3 are the first, second and third clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
LD#
Vterm = 0.75V
Vterm = 0.75V
CC#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
K
LD#
C C#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
K
BUS
MASTER
(CPU
or
ASIC)
SRAM#1
SRAM#2
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
R = 50ohms
R = 250ohms
R = 250ohms
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