PRELIMINARY
18-Mbit 4-Word Burst SRAM with DDR-I Architecture
CY7C1323AV25
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-05501 Rev. *A
Revised June 1, 2004
Features
• 18-Mbit Density (512 Kbit x 36)
• 167-MHz Clock for high bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at
333 MHz @ 167 MHz)
• Two input clocks (K and K) for precise DDR timing –
SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• 13 x 15 x 1.4mm 1.0-mm pitch fBGA package, 165 ball
(11 x 15 matrix)
• JTAG 1149.1 compatible test access port
Configuration
CY7C1323AV25 - 256K x 36
Functional Description
The CY7C1323AV25 is a 2.5V Synchronous Pipelined SRAM
equipped with DDR-I (Double Data Rate) architecture. The
DDR-I architecture consists of an SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
Addresses for Read and Write are latched on alternate rising
edges of the input (K) clock.Write data is registered on the
rising edges of both K and K. Read data is driven on the rising
edges of C and C if provided, or on the rising edge of K and K
if C/C are not provided. Every read or write operation is
associated with four words that burst sequentially into or out
of the device. The burst counter takes in the least two signif-
icant bits of the external address and bursts four 36-bit words.
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins
as the data inputs D) are tightly matched to the two output echo
clocks CQ/CQ, eliminating the need for separately capturing
data from each individual DDR SRAM in the system design.
Output data clocks(C/C) are also provided for maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1323AV25)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[35:0]
Output
Logic
Reg.
Reg.
Reg.
72
36
144
36
BWS[3:0]
Vref
Write
Reg
72
19
C
C
512K x 36 Array
Write
Reg
Write
Reg
Write
Reg
36
LD
Control
Burst
Logic
A(1:0)
A(18:2)
17
CQ
CQ
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