Errata Revision: [**]
CY7C1312V18
CY7C1314V18
CONFIDENTIAL
11/14/03
Errata Document for CY7C1312V18 & CY7C1314V18
CypressSemiconductorCorporation
•
3901NorthFirstStreet
•
SanJose
•
CA 95134
•
408-943-2600
November 2003
This document describes errata for the CY7C1312V18 and CY7C1314V18. Details include errata trigger conditions,
available workarounds, and silicon revision applicability. This document should be used as a suplement to the
existing datasheet.
Please contact your local Cypress Sales Representative if you have further questions.
Part Numbers Affected
CY7C1312V18 & CY7C1314V18 Qualification Status
These parts are currently available as Engineering Samples.
The reliability report is available on our website, www.cypress.com, QTP# 032105
CY7C1312V18 & CY7C1314V18 Errata Summary
The following table defines the errata applicability to the CY7C1312V18 and CY7C1314V18.
.
1. ADDRESS 7C ERRATA
• PROBLEM DEFINITION
In a given clock cycle:
• The read address is provided on the rising edge of K
•
The write address is provided on the rising edge of K#
• If the read and write address are the same, data is forwarded from the input port to the output port and
the data from the memory array is ignored. This feature is called the data forwarding feature and it ensures
that the most current data is always output from the device.
In the event that address 7C is the only address that changes between the read address, and the write address
in a given clock cycle, and if address 7C is changing from "1" to "0", then the data forwarding may be errone-
ously activated. The data from the memory array may be ignored and the data from the input bus may be
improperly forwarded.
• PARAMETERS AFFECTED
This errata impacts the integrity of the data. It does not impact any timing or operating parameters.
• TRIGGER CONDITION(S)
This errata can occur across all datasheet operating conditions.
Part Number
Architecture
Confguration
Clock Frequency
CY7C1312V18-133BZC
QDR-II Burst of 2
1 M x 18
133 MHz
CY7C1312V18-167BZC
QDR-II Burst of 2
1 M x 18
167 MHz
CY7C1314V18-133BZC
QDR-II Burst of 2
512 K x 36
133 MHz
CY7C1314V18-167BZC
QDR-II Burst of 2
512 K x 36
167 MHz
Items
CY7C1312V18
CY7C1314V18
Fix Status
1. Address 7C Errata
X
X
Cypress plans to fix this errata with
changes to the silicon.
2. First Clock Cycle Errata
X
X
Cypress does not plan to fix this
errata. Contact your local Cypress
sales office for additional information.
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