PRELIMINARY
CY7C1308CV25
Document #: 38-05502 Rev. *A
Page 4 of 18
address location generated by the burst counter is driven onto
the Q[35:0]. This process continues until all four 36-bit data
words have been driven out onto Q[35:0]. The requested data
will be valid 3 ns from the rising edge of the output clock (C or
C, 167-MHz device). In order to maintain the internal logic,
each Read access must be allowed to complete. Each Read
access consists of four 36-bit data words and takes two clock
cycles to complete. Therefore, Read accesses to the device
can not be initiated on two consecutive K clock rises. The
internal logic of the device will ignore the second Read
request. Read accesses can be initiated on every other K
clock rise. Doing so will pipeline the data flow such that data
is transferred out of the device on every rising edge of the
output clocks (C and C or K and K when in single clock mode).
When the read port is deselected, the CY7C1308CV25 will
first complete the pending read transactions. Synchronous
internal circuitry will automatically three-state the outputs
following the next rising edge of the positive output clock (C).
This will allow for a seamless transition between devices
without the insertion of wait states in a depth expanded
memory.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to Address inputs are stored in the Write
address register and the least two significant bits of the
address are presented to the burst counter. The burst counter
increments the address in a linear fashion. On the following K
clock rise the data presented to D[35:0] is latched and stored
into the 36-bit Write Data register provided BWS[3:0] are
asserted active. On the subsequent rising edge of the
Negative Input Clock (K) the information presented to D[35:0]
is also stored into the Write Data Register provided BWS[3:0]
are asserted active. This process continues for one more cycle
until four 36-bit words (a total of 144 bits) of data are stored in
the SRAM. The 144 bits of data are then written into the
memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the positive input clock (K). Doing
so will pipeline the data flow such that 36-bits of data can be
transferred into the device on every rising edge of the input
clocks (K and K).
When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1308CV25.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter-
mined by BWS[3:0] which are sampled with each set of 36-bit
data word. Asserting the appropriate Byte Write Select input
during the data portion of a write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a Write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1308CV25 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation.
DDR Operation
The CY7C1308CV25 enables high-performance operation
through high clock frequencies (achieved through pipelining)
and double data rate mode of operation. At slower
frequencies, the CY7C1308CV25 requires a single No
Operation (NOP) cycle when transitioning from a Read to a
Write cycle. At higher frequencies, a second NOP cycle may
be required to prevent bus contention.
If a Read occurs after a Write cycle, address and data for the
Write are stored in registers. The Write information must be
stored because the SRAM can not perform the last word Write
to the array without conflicting with the Read. The data stays
in this register until the next Write cycle occurs. On the first
Write cycle after the Read(s), the stored data from the earlier
Write will be written into the SRAM array. This is called a
Posted Write.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Echo Clocks
Echo clocks are provided on the DDR-I to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-I. CQ is referenced with respect to C and CQ is refer-
enced with respect to C. These are free-running clocks and
are synchronized to the output clock of the DDR-I. In the single
clock mode, CQ is generated with respect to K and CQ is
generated with respect to K. The timings for the echo clocks
are shown in the AC Timing table.
Programmable Impedance
An external resistor, RQ must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175
Ω and 350Ω, with
VDDQ=1.5V. The output impedance is adjusted every 1024
cycles to adjust for drifts in supply voltage and temperature.
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